This page coversMemory InterfacinginUltraScale Devicesusing theMemory Interface Generator (MIG)in theVivado Design Suite
User Guides | Date |
---|---|
UG583 -UltraScale Architecture PCB Design Guide | 06/03/2021 |
UG571 -UltraScale Architecture SelectIO Resources User Guide | 08/28/2019 |
UG572 -UltraScale Architecture Clocking Resources User Guide | 08/28/2020 |
Vivado Design Hubs | Date |
DH0007 -I/O and Clock Planning | 06/16/2021 |
DH0003 -Designing with IP | 06/16/2021 |
DH0009 -Using IP Integrator | 06/16/2021 |
Memory Interface Design Tips | Date |
PG150 -Migrating Memory Interface IP Using Vivado | 08/11/2021 |
UG583 -PCB Trace Derating | 06/03/2021 |
PG150 -Using the Memory Interface IP Traffic Generator | 08/11/2021 |
Targeted Reference Designs | Date |
DH0043 -Kintex UltraScale FPGA KCU105 Evaluation Kit | 06/16/2021 |
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Solution Centers and Known Issues | Date |
---|---|
AR34243 -Xilinx Memory Interface Solution Center | 04/26/2016 |
AR69038 -QDRII+ UltraScale and UltraScale+ IP Release Notes and Known Issues | 06/10/2020 |
Design Advisories | Date |
AR33566 -Design Advisories for Memory Interfaces | 08/25/2020 |
Debug Resources | Date |
XTP359 -Memory Interface UltraScale Design Checklist | |
AR62181 -Hardware Debug Guide - Debugging Memory Interface Issues | |
Forums | Date |
Support Community |