ISE™ CORE Generator™ IP Updates 13.3 (October 26, 2011)

General Access to Kintex™ 7 and Virtex™ 7 Low Voltage device support, Limited Access support for Artix™ 7 and Virtex 7 XT devices

• Limited Access support for the Artix 7 and Virtex 7 XT device families has been added to a selection of cores in this release. CORE Generator IP providing Limited Access support for Artix 7 and Virtex 7 XT devices display a life cycle status of "Beta" in ISE.
• For a comprehensive listing of IP cores supporting these new device families, see the table below.
  

The release also includes updates to these other popular IP cores:

• Building Block IP
  • Architecture Wizards*
  • Block Memory Generator*
  • FIFO Generator*
  • Memory Interface Generator (MIG)*
• Connectivity
  • PCI
  • PCI Express
• DSP Building Block IP
  • Floating Point Operator*
  • FFT*

*  Included at no additional charge with ISE

**Included at no additional charge with EDK

The release also includes the following new LogiCORE IP:

• Audio, Video & Image Processing
  • Chroma Resampler
• Bus Interface and IO
  • Serial RapidIO IP Gen 2
• Communications and Networking
  • JESD204
• Embedded Processing
  • AXI XADC **
• FPGA Features and Debug
  • ChipScope IBERT for Virtex-7 GTX *
• Interconnect Infrastructure
  • AXI Datamover *

• Audio, Video & Image Processing
• Basic Logic
• Communications & Networking
• Digital Signal Processing
• Embedded Processing
• FPGA Features & Debug
• Interconnect Infrastructure
• Math Functions
• Memories & Storage Elements
• Standard Bus Interfaces