2. IP 核
  3. FIR Compiler

FIR Compiler

概述

现金网博e百 描述

Finite Impulse Response (FIR) Filter 是 DSP 係統內最常見和最基礎的構建模塊之一。盡管它的算法非常簡單，但實現細節上的變異可能也很大，對於今天的硬件工程師來說，會耗費大量的時間，尤其是在數字無線電等濾波器控製係統中。FIR 編譯器不僅可縮短按下按鈕的濾波器實現時間，同時還可為用戶提供在 FIR 濾波器規範的不同硬件架構之間進行權衡的能力。

主要功能與優勢

  • 提供帶有 CORE Generator 的 VHDL 演示測試台
  • 支持基於乘法累加 (MAC) 的流水線直接形式 FIR 和基於轉置直接形式的 MACFIR
  • 高性能有限脈衝響應 (FIR)、多相抽取濾波器、多相內插器、半帶、半帶抽取濾波器和半帶內插器、Hilbert 變換和內插式濾波器實現方案
  • 高級交叉通道，有助於為高級係統實現可配置的帶寬特性
  • 支持多列 DSP48/DSP58 切片以實現對稱濾波器
  • 一個定點位精確的 C 模型，可為 Xilinx FIR 編譯器內核實現係統級分析
  • 多種實現架構：DAFIR、基於加法器結構樹的 MACFIR（適用於支持 Mult18x18 的器件）和基於加法器鏈的 MACFIR（適用於支持 XtremeDSP™ Slice 的器件）
  • Versal 器件（-1LP 速度等級）可實現高達 680MHz 的性能
  • 支持 2 -2048 抽頭
  • 為最緊湊的實現方案提供硬件折疊的自動控製
  • 支持多達 64 個通道（通道 = 獨立語音/數據/視頻流），與 FPGA 同時處理的其它流媒體內容無關。
  • 內插和抽取因子通常多達 64 個，單通道濾波器多達 1024 個
  • 支持可重新加載的係數以及達 16 個係數集
  • 係數結構自動優化，減少麵積消耗：對稱和半帶
  • 為數據及係數存儲自動選擇模塊與分布式內存
  • 與 Vivado™ IP Integrator、Vivado IP Catalog 和 AMD System Generator for DSP™ 結合使用
  • 支持超級采樣率濾波器配置
  • 與 Vivado IP Integrator、Vivado IP Catalog 和 Vitis Model Composer 聯用

資源利用率

3d狮王轮盘游戏下载

器件係列:

設計工具:

技術文檔

主要資料

Default Default 標題 文件類型 日期
開始設計

1. Choose your IP Solution

Choose the AMD FIR Compiler for applications that need a filter and a wide range of features.  For more information refer to the FIR Compiler Product Page or to the Features section of the FIR Compiler Product Guide (PG149).

2. Configure the IP

Before configuring the FIR Compiler, use a Filter Design tool, such as MATLAB®, to generate coefficients for the application.

Once you have the coefficients, configure the IP customization options. For details, the Customizing and Generating the Core section in the Design Flow Steps chapter of the FIR Compiler Product Guide (PG149).

Start by configuring the following options:

  • Filter Options Tab:
    • Filter Coefficients - Enter your coefficients generated in your Filter Design tool.
    • Filter Specification - Select the Type of Filter Implementation.
  • Channel Specification Tab:
    • Hardware Oversampling Specification.
    • Set the Input Sample Rate and the Clock Frequency.
  • Summary Tab:
    • Review the Summary of Configuration.

In addition, review the following tabs on the left side of the GUI:

  • Freq. Response: This enables you to verify that the frequency response matches your filter design requirements.
  • Implementation Details: This enables you to see the resources consumed by your filter configuration.

After the IP has been configured, generate the IP solution.

3. Generate the Example Design for a Demonstration Board

The FIR Compiler generates an example test bench along with the IP. Information on the test bench can be found in the Test Bench chapter of the FIR Compiler Product Guide (PG149). The best way to test a FIR Compiler implementation is to implement an impulse and review the impulse response in simulation. Many simulation tools allow formatting of the output in an analog format, which will give a visual view of the impulse response that can be reviewed in addition to the data response.

4. Integration

Now you are ready to integrate the FIR Compiler into your own application. The user interface is described in the Port Description section in the Product Specification chapter of the FIR Compiler Product Guide (PG149). Review the simulation in Step 3 as a reference on the expected waveforms for the interface ports.

Getting Started Resources