Xilinx 現在是 AMD 的一部分 更新的隱私條款
  2. IP 核
  3. AXI to PLBV46 Bridge

AXI to PLBV46 Bridge

簡介

现金网博e百 描述

The Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI transactions into PLBv46 transactions. It functions as 32/64-bit slave on AXI4 and 32/64-bit master on the PLB.

主要特性與優勢

  • Support AXI4 & PLB v4.6 (Xilinx simplification)
  • Supports 1:1 (AXI:PLB) synchronous clock ratio
  • Support 32-bit address on AXI & PLB interfaces
  • Supports 32/64-bit data buses on AXI & PLB interfaces (1:1 ratio)
  • Supports Write and read data buffering

資源利用

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