logiCVC-ML Compact Multilayer Video Controller

  • 现金网博e百 編號:logiCVC-ML
  • 供應商:Xylon d.o.o.
  • Premier Partner

现金网博e百 描述

The logiCVC-ML IP core is an advanced display graphics controller that enables an easy video and graphics integration into embedded systems with the Xilinx SoC, MPSoC and FPGA devices. It can be used as a standalone graphics IP core, or as a part of larger graphics systems along with other Xylon logicBRICKS IP cores. The logiCVC-ML is a real plug-and-play IP core, prepared for Xilinx Vivado Design Suite, and designers familiar with these tools can immediately start designing. The IP's size and features can be easily adjusted through IP drag and drop tools GUI interface. The logiCVC-ML comes ready-to-use and with the rich set of deliverables including SW driver and documentation. Currently Xylon offers software drivers for use with Linux®, Android(TM) and Microsoft® Windows® Embedded Compact operating systems. Free Xylon reference design for popular Zynq-7000 SoC based development kits enable quick and risk-free evaluation.


主要特性與優勢

  • Supported output formats: Parallel RGB, Parallel YUV, PAL/NTSC, LVDS, Camera link, DVI
  • Configurable AMBA AXI4, AXI4-Lite and AXI4-Stream interfaces
  • Pixel, Layer, or Color Lookup Table (CLUT) alpha blending
  • Configurable layer's size, position and offset
  • Supports up to 5 layers
  • Up to 8192x8192 display resolutions (including 4K2K@60)
  • Supports LCD TFT and CRT displays
  • Software drivers for Linux, Android and Microsoft Windows Embedded Compact
  • Free reference designs: logiREF-ZGPU-ZC702, logiREF-ZGPU-ZC706, logiREF-ZGPU-ZED

特色技術文檔

器件實現矩陣

麵向此核實現範例的器件使用矩陣。聯係供應商了解更多信息。

係列 器件 速度等級 工具版本 硬件驗證? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado ML 2021.1 Y 0 908 8 0 0 0 333
VERSAL_AI_CORE Family XCVC1902 -1 Vivado 2019.1 Y 0 1235 7 10 0 0 200
KINTEX-7 Family XC7K355T -2 Vivado 2018.2 Y 285 477 1 0 0 0 200
ARTIX-7 Family XC7A100T -2 Vivado 2018.2 Y 283 443 1 0 0 0 130
Zynq-7000 Family XC7Z020 -1 Vivado 2016.2 Y 281 489 1 0 0 0 220
Spartan 6 Family XC6SLX25 -3 Vivado 2014.4 Y 411 808 2 0 0 0 206
VIRTEX6LXT Family XC6VLX75T -1 Vivado 2014.4 Y 394 681 767 0 0 0 200

IP 質量指標

綜合信息

數據創建日期 Feb 16, 2022
當前 IP 修訂號 5.5.2
當前修訂日期已發布 Jan 20, 2022
第一版發布日期 Apr 09, 2010

Xilinx 客戶的生產使用情況

Xilinx 客戶成功生產項目的數量 80
可否提供參考? Y

交付內容

可供購買的 IP 格式 Bitstream, Netlist, Source Code
源代碼格式 VHDL
是否包含高級模型? N
提供集成測試台 Y
集成測試台格式 VHDL
是否提供代碼覆蓋率報告? N
是否提供功能覆蓋率報告? N
是否提供 UCF? UCF
商業評估板是否可用? Y
評估板所用的 FPGA Zynq UltraScale+ MPSoC
是否提供軟件驅動程序? Y
驅動程序的操作係統支持 Linux, WEC7, Android

實現方案

代碼是否針對 Xilinx 進行優化? Y
標準 FPGA 優化技術 Inference, Instantiation
所支持的綜合軟件工具及版本 Xilinx XST
是否執行靜態時序分析? Y
AXI 接口 AXI4, AXI4-Lite
是否包含 IP-XACT 元數據? N

驗證

是否有可用的文檔驗證計劃? Yes, document only plan
測試方法 Directed Testing
斷言 Y
收集的覆蓋指標 None
是否執行時序驗證? Y
可用的時序驗證報告 N
所支持的仿真器 Mentor ModelSIM

硬件驗證

在 FPGA 上進行驗證 Y
所使用的硬件驗證平台 ZCU102, ZC702