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描述
The logiWIN IP core accepts a streaming video input, decodes it and converts into the RGB format. The input video can be real-time scaled, de-interlaced, cropped and positioned on the video display. Captured video can be processed by various IP cores and displayed by a graphics controller IP, i.e. the logiCVC-ML Compact Multilayer Video Controller LCD display controller IP core from Xylon. The logiWIN integrates high-quality anti-aliasing algorithm that guarantees high picture quality without visible artifacts. The core is fully embedded into Xilinx Vivado and ISE Design Suites, and its usage does not require skills beyond general Xilinx tools knowledge. Parametrizable VHDL design allows tuning of slice consumption and features set through implementation tools GUI interface. Instantiations of multiple logiWIN IPs enable processing of multiple video inputs within a single Xilinx FPGA device. To enable an easy IP evaluation, Xylon offers a number of free reference designs for the most popular Zynq-7000 SoC based development boards.
主要特性與優勢
- Double or triple buffering for video flicker prevention
- Provides Bob ad Weave de-interlacing algorithms
- Maximum input and output resolutions are 2048x2048
- Supports Pixel Alpha blending
- Supported busses: AMBA AXI4 and Xylon XMB
- Video input cropping and smooth image positioning
- Image color enhancements: brightness, contrast, hue, saturation
- Output video formats: RGB ad YCbCr
- Input video formats: RGB, ITU656 (PAL/NTSC), ITU1120, YUV4:2:2
- Real-time video scale-up and scale down
特色技術文檔
