Overview
Versal AI Engine Development using Vitis Model Composer
Vitis™ Model Composer enables the rapid simulation, exploration, and code generation of algorithms targeted for Versal AI Engines from within the Simulink environment. You can achieve this by using the AI Engine library blocks or by importing kernels and data-flow graphs into Vitis Model Composer as blocks and controlling the behavior of the kernels and graphs by configuring the block GUI parameter. The tool also allows you to model and simulate a design with a mix of AI Engine and Programmable logic (HDL/HLS) blocks. Simulation results can be visualized by seamlessly connecting Simulink source and sink blocks with Vitis Model Composer AI Engine blocks.
Vitis Model Composer provides a set of performance-optimized blocks for use within the Simulink environment. These include:
AI Engine blocks
- Includes a set of complex AI Engine DSP building blocks related to FIR, FFT, DDS, and mixers.
- Contains blocks to import kernels and graphs that can be targeted to the AI Engine portion of Versal devices.
HLS (Targeting PL and generates HLS code)
- Offers predefined blocks that include functional blocks for math, linear algebra, logic, and bit-wise operations
- Block to import HLS kernels which can be targeted to the PL portion of Versal devices.
HDL (Targeting PL and generates RTL code)
- Blocks to model logic, math, and DSP elements and synthesize them on an FPGA
- Includes a FIR Compiler block that targets the dedicated DSP48E1, DSP48E2 hardware resources in Versal design
- Blocks that support connection between the AI Engine and the AMD HDL blockset.
Videos
Learn to program Versal AI Engines using Vitis Model Composer
Designing Versal AI Engines Using Simulink and Vitis Model Composer
This 20-minute video shows how the Simulink tool and Vitis Model Composer can be used to model, simulate, and optimize a FIR filter on an AI Engine array.
Implementing FIR Filters in Versal Adaptive SoC Devices
This video provides an overview for system architects and engineers covering FIR filter implementation in Versal Adaptive SoC devices.
AI Engine Development Using Vitis Model Composer
This 30-minute video introduces the Vitis Model Composer tool and how to design AI Engine applications using the AI Engine DSP library.
Early FPGA/SoC Design Verification with Simulink and the Vivado Simulator
This webinar shows how to perform FPGA/SoC design verification using the Simulink® tool and the Vivado™ simulator.
Design Examples
Explore design examples on how to use Vitis Model Composer blocks
AI Engine Examples
| Importing Kernels and Graphs | Run time parameters (RTP) | DSP Functions |
|---|---|---|
| Importing a kernel class as a block | A design with a scalar RTP input | Filtering in frequency domain |
| Importing a graph as a block | A design with an asynchronous vector RTP input | Stream based FFT running at 2 GSPS |
| FIR with 4Gsps throughput | ||
| Dual stream SSR FIR at 16 GSPS | ||
| Dynamic Point FFT |
PL + AI Engine Design Examples
| HLS + AI Engine | HDL + AI Engine |
|---|---|
| Channelizer | Multi-rate design |
| 2D FFT | Single Stream SSR FIR with PL |
| 2D FFT |
GitHub Tutorials
Access tutorials on AI Engine Library, HLS and HDL
AI Engine Library
- Lab 1: Introduction to Versal™ Adaptive and AI Engine
- Lab 2: Build and Simulate an AI Engine Design
- Lab 3: Import Custom AI Engine code
- Lab 4 : AI Engine Code Generation and Cycle- Approximate Simulation
- Lab 5 : AI Engine Designs in Vitis Analyzer
- Lab 6 : Hardware Validation of Versal Adaptive design
HLS Library
These tutorials help you examine the Vitis Model Composer HLS library, build a simple design using HLS blocks, and learn about the data types supported by Vitis Model Composer.
HDL Library
These tutorials show you how to use the Vitis Model Composer HDL library to specify a design in Simulink® and synthesize the design into an FPGA.
Resources
Vitis Model Composer: A MATLAB and Simulink-Based Product
This course provides experience with using the Vitis™ Model Composer tool for model-based designs.
AI Engine DSP Library and Model Composer
This live online course provides experience with using the Vitis™ Model Composer tool for model-based designs.
Vitis Model Composer GitHub Repository
Explore the Github repository to learn more about rapid design using Vitis™ Model Composer.