Resource Utilization for Distributed Memory Generator v8.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Artix-7

Part Information			Configuration Parameters																											Resource Utilization
Device	Package	Speed Grade	Configuration Name	depth	data_width	memory_type	input_options	input_clock_enable	qualify_we_with_i_ce	dual_port_address	simple_dual_port_address	output_options	Pipeline_Stages	common_output_clk	single_port_output_clock_enable	common_output_ce	dual_port_output_clock_enable	simple_dual_port_output_clock_enable	coefficient_file	default_data_radix	default_data	reset_qspo	reset_qdpo	reset_qsdpo	sync_reset_qspo	sync_reset_qdpo	sync_reset_qsdpo	ce_overrides	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a100t	fgg676	-1	dmg_a7_sram_24353_0	144	8	single_port_ram	registered	true	true	non_registered	non_registered	non_registered	0	false	false	false	false	false	no_coe_file_loaded	16	a7	false	false	false	false	false	false	ce_overrides_sync_controls	clk=50	33	17	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a100t	fgg676	-1	dmg_a7_sram_24353_1	80	8	dual_port_ram	registered	true	true	non_registered	non_registered	non_registered	0	false	false	false	false	false	no_coe_file_loaded	10	86	false	false	false	false	false	false	ce_overrides_sync_controls	clk=50	41	16	0	0	0	PRODUCTION 1.23 2018-06-13

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