Performance and Resource Utilization for DFX Decoupler v1.0

Vivado Design Suite Release 2022.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
Number of interfaces
Interface VLNV
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t fbg676 1 xc7k325tfbg676-1_0 1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 1331 2 1 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_1 0 1 1 xilinx.com:signal:data_rtl:1.0 aclk 704 14 7 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_2 1 0 1 xilinx.com:interface:aximm_rtl:1.0 aclk 1296 7 1 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_3 1 0 1 xilinx.com:interface:axis_rtl:1.0 aclk 1325 3 1 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
Number of interfaces
Interface VLNV
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku040 fbva676 1 xcku040-fbva676-1-i_0 1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 1489 2 1 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_1 0 1 1 xilinx.com:signal:data_rtl:1.0 aclk 875 12 7 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_2 1 0 1 xilinx.com:interface:aximm_rtl:1.0 aclk 1472 7 1 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_3 1 0 1 xilinx.com:interface:axis_rtl:1.0 aclk 1472 3 1 0 0 0 PRODUCTION 1.25 12-04-2018

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
Number of interfaces
Interface VLNV
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_0 1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 1325 2 1 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_1 0 1 1 xilinx.com:signal:data_rtl:1.0 aclk 681 13 7 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_2 1 0 1 xilinx.com:interface:aximm_rtl:1.0 aclk 1290 7 1 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_3 1 0 1 xilinx.com:interface:axis_rtl:1.0 aclk 1325 3 1 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
Number of interfaces
Interface VLNV
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_0 1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 1641 2 1 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_1 0 1 1 xilinx.com:signal:data_rtl:1.0 aclk 1202 12 7 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_2 1 0 1 xilinx.com:interface:aximm_rtl:1.0 aclk 1624 7 1 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_3 1 0 1 xilinx.com:interface:axis_rtl:1.0 aclk 1624 3 1 0 0 0 PRODUCTION 1.26 12-04-2018

Zynq-7000

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
HAS_AXIS_CONTROL
HAS_AXI_LITE
Number of interfaces
Interface VLNV
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7z045 fbg676 1 xc7z045fbg676-1_0 1 0 1 xilinx.com:signal:data_rtl:1.0 aclk 1325 2 1 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_1 0 1 1 xilinx.com:signal:data_rtl:1.0 aclk 735 15 7 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_2 1 0 1 xilinx.com:interface:aximm_rtl:1.0 aclk 1290 7 1 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_3 1 0 1 xilinx.com:interface:axis_rtl:1.0 aclk 1325 3 1 0 0 0 PRODUCTION 1.12 2019-11-22

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