Performance and Resource Utilization for AXI4-Stream Interconnect RTL v1.1

Vivado Design Suite Release 2024.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SWITCH_TDATA_NUM_BYTES
HAS_TSTRB
HAS_TLAST
HAS_TID
M00_AXIS_TDATA_NUM_BYTES
C_S00_AXIS_REG_CONFIG
S00_AXIS_TDATA_NUM_BYTES
S00_AXIS_FIFO_MODE
C_S00_AXIS_FIFO_DEPTH
Fixed clocks (MHz) Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 2 Data FIFO: 16 depth, 128-bit 16 false false false 16 16 1_(Normal) 16 inst/M00_AXIS_ACLK=730 inst/S00_AXIS_ACLK=730 *ACLK 730 119 332 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 2 Data FIFO: 128 depth, 128-bit 16 false false false 16 16 1_(Normal) 128 inst/M00_AXIS_ACLK=489 inst/S00_AXIS_ACLK=489 *ACLK 489 51 210 0 2 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 2 Data FIFO: 512 depth, 128-bit 16 false false false 16 16 1_(Normal) 512 inst/M00_AXIS_ACLK=505 inst/S00_AXIS_ACLK=505 *ACLK 505 67 220 0 2 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 2 Data width converter: 512-bit to 128-bit 16 false false false 16 64 inst/M00_AXIS_ACLK=752 inst/S00_AXIS_ACLK=752 *ACLK 752 313 733 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 2 Register slice: 32-bit 4 false false false 4 1 4 inst/M00_AXIS_ACLK=975 inst/S00_AXIS_ACLK=975 *ACLK 975 48 83 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 2 Register slice: 128-bit 16 false false false 16 1 16 inst/M00_AXIS_ACLK=790 inst/S00_AXIS_ACLK=790 *ACLK 790 156 299 0 0 0 PRODUCTION 1.26 12-04-2018

COPYRIGHT

Copyright 2024 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.