Resource Utilization for AXI4-Stream Accelerator Adapter v2.1

Vivado Design Suite Release 2015.3

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation in Vivado Design Suite.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2015.3 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Virtex-7

Part Information			Configuration Parameters												Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_M_AXIS_TDATA_WIDTH	C_S_AXIS_TDATA_WIDTH	C_N_OUTPUT_ARGS	C_N_INPUT_ARGS	C_N_INPUT_SCALARS	C_N_OUTPUT_SCALARS	C_N_INOUT_SCALARS	C_OARG_HAS_BRAM	C_OARG_HAS_FIFO	C_PRMRY_IS_ACLK_ASYNC	Fixed clocks (MHz)	LUTs	FFs	LUT-FF Pairs	DSP48s	36k BRAMs	18k BRAMs	Speedfile Status
xc7v2000t	flg1925	-1	core_implemented	32	32	1	1				1	1	1	aclk=83 m_axis_aclk=83 s_axi_aclk=100 s_axis_aclk=83	435	746	655	0	8	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-1	core_implemented_1	32	64	1	2				1	1	1	aclk=83 m_axis_aclk=83 s_axi_aclk=100 s_axis_aclk=83	485	865	737	0	12	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-1	core_implemented_2	32	64	2	1				1	1	1	aclk=83 m_axis_aclk=83 s_axi_aclk=100 s_axis_aclk=83	600	1032	926	0	12	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-1	core_implemented_3	64	64	4	4				1	1	1	aclk=83 m_axis_aclk=83 s_axi_aclk=100 s_axis_aclk=83	1048	2080	1784	0	32	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-1	core_implemented_4	64	64	0	0			5	1	1	1	aclk=83 s_axi_aclk=100	1126	2380	2058	0	0	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-1	core_implemented_5	64	64	3	3	3	6		1	1	1	aclk=83 m_axis_aclk=83 s_axi_aclk=100 s_axis_aclk=83	1710	3480	3028	0	24	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-1	core_implemented_6	32	32	8	8	0	0		1	1	1	aclk=83 m_axis_aclk=83 s_axi_aclk=100 s_axis_aclk=83	1863	3589	2977	0	64	0	PRODUCTION 1.10 2014-09-11
xc7v2000t	flg1925	-1	core_implemented_7	32	32	1	2	8	8		1	1	1	aclk=83 m_axis_aclk=83 s_axi_aclk=100 s_axis_aclk=83	1925	4209	3579	0	12	0	PRODUCTION 1.10 2014-09-11

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