Performance and Resource Utilization for Avalon Master Bridge v1.0

Vivado Design Suite Release 2018.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2018.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Virtex-7
Zynq-7000

Kintex-7

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_AVA_ADDR_WIDTH	C_NUM_MASTERS	C_AVA_DATA_WIDTH	C_MODE	C_ENABLE_PIPELINE	C_AVA_BYTEENABLES	Clock Input	Fmax (MHz)	LUTs	FFs	LUT-FF Pairs	DSP48s	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	-3	k7_4Master_ReadWrite_1	32	4	32	2	0	0	clk	382	1235	864	551	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_oneMaster_ReadOnly_1	32	1	32	0	0	0	clk	523	314	354	188	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_oneMaster_ReadWrite_1_1024	32	1	1024	2	0	0	clk	413	2326	3169	1772	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_oneMaster_ReadWrite_1_128	32	1	128	2	0	0	clk	444	939	1034	586	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_oneMaster_ReadWrite_1_256	32	1	256	2	0	0	clk	429	1145	1341	751	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_oneMaster_ReadWrite_1_32	32	1	32	2	0	0	clk	491	757	786	439	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_oneMaster_ReadWrite_1_512	32	1	512	2	0	0	clk	398	1563	1950	1094	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_oneMaster_ReadWrite_1_64	32	1	64	2	0	0	clk	460	828	873	500	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_oneMaster_WriteOnly_1	32	1	32	1	0	0	clk	491	451	435	254	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_onemaster_allEnable_conf__1	32	1	32	2	1	1	clk	319	1093	1209	627	0	2	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	k7_onemaster_pipelineEnable_conf__1	32	1	32	2	1	0	clk	491	801	751	438	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_AVA_ADDR_WIDTH	C_NUM_MASTERS	C_AVA_DATA_WIDTH	C_MODE	C_ENABLE_PIPELINE	C_AVA_BYTEENABLES	Clock Input	Fmax (MHz)	LUTs	FFs	LUT-FF Pairs	DSP48s	36k BRAMs	18k BRAMs	Speedfile Status
xcku035	fbva900	-3	ku_4Master_ReadWrite_1	32	4	32	2	0	0	clk	516	1193	866	551	0	0	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_oneMaster_ReadOnly_1	32	1	32	0	0	0	clk	713	312	354	182	0	0	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_oneMaster_ReadWrite_1_1024	32	1	1024	2	0	0	clk	440	2304	3167	1738	0	0	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_oneMaster_ReadWrite_1_128	32	1	128	2	0	0	clk	636	965	1032	585	0	0	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_oneMaster_ReadWrite_1_256	32	1	256	2	0	0	clk	615	1150	1339	733	0	0	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_oneMaster_ReadWrite_1_32	32	1	32	2	0	0	clk	625	771	786	438	0	0	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_oneMaster_ReadWrite_1_512	32	1	512	2	0	0	clk	494	1563	1949	1083	0	0	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_oneMaster_ReadWrite_1_64	32	1	64	2	0	0	clk	625	838	873	491	0	0	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_oneMaster_WriteOnly_1	32	1	32	1	0	0	clk	647	453	435	253	0	0	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_onemaster_allEnable_conf__1	32	1	32	2	1	1	clk	396	1129	1207	628	0	2	0	PRODUCTION 1.24.01 01-12-2017
xcku035	fbva900	-3	ku_onemaster_pipelineEnable_conf__1	32	1	32	2	1	0	clk	636	816	751	441	0	0	0	PRODUCTION 1.24.01 01-12-2017

Kintex UltraScale+

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_AVA_ADDR_WIDTH	C_NUM_MASTERS	C_AVA_DATA_WIDTH	C_MODE	C_ENABLE_PIPELINE	C_AVA_BYTEENABLES	Clock Input	Fmax (MHz)	LUTs	FFs	LUT-FF Pairs	DSP48s	36k BRAMs	18k BRAMs	Speedfile Status
xcku13p	ffve900	-3	kup_4Master_ReadWrite_1	32	4	32	2	0	0	clk	680	1184	866	559	0	0	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_oneMaster_ReadOnly_1	32	1	32	0	0	0	clk	910	316	354	183	0	0	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_oneMaster_ReadWrite_1_1024	32	1	1024	2	0	0	clk	615	2311	3167	1741	0	0	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_oneMaster_ReadWrite_1_128	32	1	128	2	0	0	clk	855	964	1032	577	0	0	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_oneMaster_ReadWrite_1_256	32	1	256	2	0	0	clk	822	1164	1339	748	0	0	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_oneMaster_ReadWrite_1_32	32	1	32	2	0	0	clk	877	769	786	435	0	0	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_oneMaster_ReadWrite_1_512	32	1	512	2	0	0	clk	713	1567	1949	1080	0	0	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_oneMaster_ReadWrite_1_64	32	1	64	2	0	0	clk	855	842	873	490	0	0	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_oneMaster_WriteOnly_1	32	1	32	1	0	0	clk	844	454	435	249	0	0	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_onemaster_allEnable_conf__1	32	1	32	2	1	1	clk	527	1151	1207	643	0	2	0	ADVANCE 1.18.1 12-07-2017
xcku13p	ffve900	-3	kup_onemaster_pipelineEnable_conf__1	32	1	32	2	1	0	clk	888	825	751	439	0	0	0	ADVANCE 1.18.1 12-07-2017

Virtex-7

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_AVA_ADDR_WIDTH	C_NUM_MASTERS	C_AVA_DATA_WIDTH	C_MODE	C_ENABLE_PIPELINE	C_AVA_BYTEENABLES	Clock Input	Fmax (MHz)	LUTs	FFs	LUT-FF Pairs	DSP48s	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	-1	v7_4Master_ReadWrite_1	32	4	32	2	0	0	clk	288	1145	864	544	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_oneMaster_ReadOnly_1	32	1	32	0	0	0	clk	382	313	354	187	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_oneMaster_ReadWrite_1_1024	32	1	1024	2	0	0	clk	273	2281	3169	1745	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_oneMaster_ReadWrite_1_128	32	1	128	2	0	0	clk	319	933	1034	578	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_oneMaster_ReadWrite_1_256	32	1	256	2	0	0	clk	319	1125	1341	741	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_oneMaster_ReadWrite_1_32	32	1	32	2	0	0	clk	350	750	786	438	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_oneMaster_ReadWrite_1_512	32	1	512	2	0	0	clk	304	1556	1950	1089	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_oneMaster_ReadWrite_1_64	32	1	64	2	0	0	clk	335	823	873	495	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_oneMaster_WriteOnly_1	32	1	32	1	0	0	clk	335	449	435	257	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_onemaster_allEnable_conf__1	32	1	32	2	1	1	clk	210	1063	1209	616	0	2	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	-1	v7_onemaster_pipelineEnable_conf__1	32	1	32	2	1	0	clk	366	795	751	444	0	0	0	PRODUCTION 1.12 2014-09-11

Zynq-7000

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_AVA_ADDR_WIDTH	C_NUM_MASTERS	C_AVA_DATA_WIDTH	C_MODE	C_ENABLE_PIPELINE	C_AVA_BYTEENABLES	Clock Input	Fmax (MHz)	LUTs	FFs	LUT-FF Pairs	DSP48s	36k BRAMs	18k BRAMs	Speedfile Status
xc7z100	ffg1156	-2	z7_4Master_ReadWrite_1	32	4	32	2	0	0	clk	366	1233	864	558	0	0	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_oneMaster_ReadOnly_1	32	1	32	0	0	0	clk	475	315	354	189	0	0	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_oneMaster_ReadWrite_1_1024	32	1	1024	2	0	0	clk	366	2322	3169	1768	0	0	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_oneMaster_ReadWrite_1_128	32	1	128	2	0	0	clk	413	938	1034	582	0	0	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_oneMaster_ReadWrite_1_256	32	1	256	2	0	0	clk	398	1130	1341	741	0	0	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_oneMaster_ReadWrite_1_32	32	1	32	2	0	0	clk	460	756	786	437	0	0	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_oneMaster_ReadWrite_1_512	32	1	512	2	0	0	clk	366	1559	1950	1092	0	0	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_oneMaster_ReadWrite_1_64	32	1	64	2	0	0	clk	444	830	873	500	0	0	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_oneMaster_WriteOnly_1	32	1	32	1	0	0	clk	444	451	435	256	0	0	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_onemaster_allEnable_conf__1	32	1	32	2	1	1	clk	273	1081	1209	620	0	2	0	PRODUCTION 1.11 2014-09-11
xc7z100	ffg1156	-2	z7_onemaster_pipelineEnable_conf__1	32	1	32	2	1	0	clk	444	801	751	441	0	0	0	PRODUCTION 1.11 2014-09-11

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