References
- SDAccel™Development Environment web page
- Vivado® Design SuiteDocumentation
- Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator(UG994)
- Vivado Design Suite User Guide: Creating and Packaging Custom IP(UG1118)
- Vivado Design Suite User Guide: Partial Reconfiguration(UG909)
- Vivado Design Suite User Guide: High-Level Synthesis(UG902)
- UltraFast Design Methodology Guide for the Vivado Design Suite(UG949)
- Vivado Design Suite Properties Reference Guide(UG912)
- Khronos Group web page: Documentation for the OpenCL standard
- Xilinx®Virtex® UltraScale+™FPGA VCU1525 Acceleration Development Kit
- Xilinx®Kintex® UltraScale™FPGA KCU1500 Acceleration Development Kit
- Xilinx®Alveo™web page