JTAG Fallback for Private Debug Network

RTL kernel and platform debug in a data center environment typically uses the XVC-over-PCIe®connection due to the typical inaccessibility of the physical JTAG connector of the board. While XVC-over-PCIeallows you to remotely debug your systems, certain debug scenarios such as AXI interconnect system hangs can prevent you from accessing the design debug functionality that depends on thesePCIe/AXI features. Being able to debug these kinds of scenarios is especially important for platform designers.

TheJTAG Fallbackfeature is designed to provide access to debug networks that were previously only accessible through XVC-over-PCIe. TheJTAG Fallbackfeature can be enabled without having to change the XVC-over-PCIe-based debug network in the platform design.

On the host side, when theVivado®user connects throughhw_serverto a JTAG cable that is connected to the physical JTAG pins of the device under test (DUT),hw_serverdisables the XVC-over-PCIepathway to the DUT. When you disconnect from the JTAG cable, hw_server re-enables the XVC-over-PCIepathway to the DUT.