Configuring the System Architecture

By default, a single hardware instance is implemented from a kernel. If the host intends to execute the same kernel multiple times, then multiple such kernel executions take place on the same hardware instance sequentially. However, you can customize the kernel compilation (linking stage) to create multiple hardware instances from a single kernel. This can improve execution performance as the multiple kernel calls can now run concurrently, overlapping their execution while running on separate hardware instances.

Multiple instances of the kernel can be created by using thexocc -–nkswitch during linking.

For example, for a kernel namefoo, two hardware instances can be implemented as follows:

# xocc -–nk : xocc --nk foo:2

By default, the implemented instance names are_1and_2. However, you can optionally change the default instance names as shown below:

# xocc -–nk ::.… xocc --nk foo:3:fooA.fooB.fooC

This example implements three identical copies, or hardware instances of kernelfoo, namedfooA,fooB, andfooCon the FPGA programmable logic.

By default, all the memory interfaces from all the kernels are connected to a single global memory bank. As a result, only one memory interface at a time can transfer data to and from the memory bank, limiting the performance of the kernel. If the FPGA contains only one DDR (or global) memory bank, this is the only option.

However, some FPGA devices contain multiple DDR memory banks. You can customize the connections among the kernel memory interfaces and the DDR memory bank of such a device by altering the default connection.

The above approach can even improve the performance of a single kernel.

Consider the following example:

void cnn( int *image, // Read-Only Image int *weights, // Read-Only Weight Matrix int *out, // Output Filters/Images ... // Other input or Output ports #pragma HLS INTERFACE m_axi port=image offset=slave bundle=gmem #pragma HLS INTERFACE m_axi port=weights offset=slave bundle=gmem #pragma HLS INTERFACE m_axi port=out offset=slave bundle=gmem

The example shows two memory interface inputs for the kernel:imageandweights. If both are connected to the same DDR bank, a concurrent transfer of both of these inputs into the kernel is not possible.

The following steps are needed to implement separate DDR bank connections for theimageandweightsinputs:

1. Specify separate bundle names for these inputs. This is discussed inMemory Data Inputs and Outputs. However, for reference the code is shown here again.

   void cnn( int *image, // Read-Only Image int *weights, // Read-Only Weight Matrix int *out, // Output Filters/Images ... // Other input or Output ports #pragma HLS INTERFACE m_axi port=image offset=slave bundle=gmem #pragma HLS INTERFACE m_axi port=weights offset=slave bundle=gmem1 #pragma HLS INTERFACE m_axi port=out offset=slave bundle=gmem

   IMPORTANT:When specifying a bundle=name, you should use all lowercase characters to be able to assign it to a specific memory bank using the --spoption.

   The memory interface inputsimageandweightsare assigned different bundle names in the example above.

2. Alter the XOCC link process to create custom DDR bank connections. This is done using-–spswitch:

   --sp .:

   Where:

   • is the instance name of the kernel as specified by the--nkoption, described inMultiple Instances of a Kernel.
   • is the name of the interface bundle defined by the HLS INTERFACE pragma, includingm_axi_as a prefix, and thebundle=name when specified.
     TIP:If the port is not specified as part of a bundle, then the is the specified port=name, without the m_axi_prefix.
   • is denoted asbank0,bank1, etc. For a device with four DDR banks, the bank names arebank0,bank1,bank2, andbank3.

   For the above example, considering a single instance of thecnnkernel, the-–spswitch can be specified as follows:

   --sp cnn_1.m_axi_gmem:bank0 \ -–sp cnn_1.m_axi_gmem1:bank1

The customized bank connection needs to be reflected in the host code as well. This was previously discussed inSpecifying Exact Memory from the Host Code.