Release Notes
What's New for 2018.3
The 2018.3 release of theSDAccel™development environment provides support for theXilinx®Alveo™U200 and U250 Data Center accelerator cards, as well as the VCU1525 acceleration platform.
IMPORTANT:In the 2018.3 release (as in the 2018.2.xdf release), the Xilinx Runtime (XRT), the deployment shell to program the card, and the development shell to develop applications, are all delivered as separate installable Linux packages for each supported platform. Users who simply wish to install an accelerator card, and deploy applications to run on an accelerator card, may get started as described in
Getting Started withAlveoData Center Accelerator Cards(UG1301), or the
VCU1525 Reconfigurable Acceleration Platform User Guide(UG1268). Users who want to use the complete
SDAcceldevelopment environment for programming, compiling, and debugging accelerated applications, must do a full installation as described in
SDAccel Environment Installation.
Enhancements to U200, U250, and VCU1525 Platforms
- A redesigned static portion to better route signals to super logic regions (SLRs).
- Updated Shells and XRT to move the Management Function to Physical Function 0 (PF0) and User Function to Physical Function 1 (PF1).
- An optional memory resource constructed from memory primitives in the programmable logic fabric is now available, called Programmable Logic Random Access Memory (PLRAM).
SDAccelTool Enhancements
- TheSDAccellinker has a new option (
xocc --slr
) to manually assign compute units to specific SLRs. This feature will only work on compatible platforms. - In addition to DDR banks, the host application can access PLRAM for direct data transfer with a kernel. This feature is enabled using the
xocc --sp
option with compatible platforms. - Command line users can use the graphical user interface (GUI) to browse results and view graphical timelines.
- This release also provides improved visualization and profiling features.
- NewOpenCL™pragmas have been added:
xcl_loop_tripcount
xcl_latency
xcl_pipeline_loop(II)
- Enhanced debug features for data center applications.
- Ability to exportSDAccelkernels directly from standalone high-level synthesis (HLS) projects.
- Comprehensive management and querying of xclbin and platform metadata with the new xclbinutil utility.
Changed Behavior
Migrating from 2018.2
Area | 2018.2 Behavior | Changes for 2018.3, or 2018.2.xdf |
---|---|---|
Installation | xbinst andxbsak utilities were used to install and manage accelerator cards. |
xbutil program replaces bothxbsak andxbinst for installing and managing accelerator cards. |
Command-line flow | Sourcesettings64.sh as needed to setup the environment for running theSDAccelGUI or command-line tools. |
Source bothsettings64.sh and/opt/xilinx/xrt/setup.sh for proper command-line compilation. |
Linking | The--sp option requires specifying DDR banks using bank0, bank1... |
The--sp option has been changed to specify the DDR banks as DDR[0], DDR[1], and to support the use of PLRAM. |
Runtime | The order ofclCreateProgramWithBinary andclCreateBuffer in the host application was not checked. |
The order ofclCreateProgramWithBinary andclCreateBuffer in the host application is checked, andclCreateProgramWithBinary must occur beforeclCreateBuffer , or else a runtime error will occur. |
RTL Kernels | RTL Kernels created manually could have register addresses in a reserved space. | The RTL kernel wizard always starts the kernel input arguments at address 0x10, locations below this are reserved. A control register is required by all register transfer level (RTL) kernels at base address 0x0. Registers at base address 0x4, 0x8, and 0xC are used if kernel interrupts are enabled. You must update any RTL kernels created prior to 2018.3 if they use register addresses below 0x10. |
KCU1500 | The KCU1500 platform was delivered as part of the release installation. | The KCU1500 board is not delivered as part of the release installation. However, a KCU1500 card previously installed from the 2018.2 release is supported for use with the 2018.3 release. |
Licensing | Solaris operating system supported. | To useSDAccel2018.3, you must upgrade your license server tools to Flex 11.14.1 versions. For more information, seeLicense Management Tools - 2018.3 |
Prior Release Notes
For more information on prior changes, refer to the Release Notes for the release:
Supported Platforms in 2018.3
TIP:The term and acronym
Device Support Archive (DSA)has been deprecated in the 2018.3 release. The term DSA is replaced by:
- Deployment Shell— for users who will only run applications on the accelerator card.
- Development Shell— for users who will develop an application using theSDAcceldevelopment environment.
Area | SLR 0 | SLR 1 | SLR 2 |
---|---|---|---|
General information | |||
SLR description | Bottom of device; dedicated to dynamic region. | Middle of device; shared by dynamic and static region resources. | Top of device; dedicated to dynamic region. |
XOCC link syntax for compute unit placement1 | --slr |
--slr |
--slr |
Global memory resources available in dynamic region3 | |||
DDR Memory channels (system port name) | DDR[0] (16 GB DDR4) | DDR[1] (16 GB DDR4, in static region) DDR[2] (16 GB DDR4, in dynamic region) |
DDR[3] (16 GB DDR4) |
PLRAM memory channels (system port name) | PLRAM[0] (128K, BRAM) | PLRAM[1] (128K BRAM) | PLRAM[2] (128K BRAM) |
Approximate available fabric resources in dynamic region | |||
CLB LUT | 354K | 159K | 354K |
CLB Register | 723K | 328K | 723K |
Block RAM Tile | 638 | 326 | 638 |
URAM | 320 | 160 | 320 |
DSP | 2265 | 1317 | 2265 |
|
Area | SLR 0 | SLR 1 | SLR 2 | SLR 3 |
---|---|---|---|---|
General information | ||||
SLR description | Shared by dynamic and static region resources. | Shared by dynamic and static region resources. | Shared by dynamic and static region resources. | Shared by dynamic and static region resources. |
XOCC link syntax for compute unit placement1 | --slr |
--slr |
--slr |
--slr |
Global memory resources available in dynamic region3 | ||||
DDR memory channels (system port name) | DDR[0] (16GB DDR4) | DDR[1] (16GB DDR4) | DDR[2] (16GB DDR4) | DDR[3] (16GB DDR4) |
PLRAM memory channels (system port name) | PLRAM[0] (128K BRAM) | PLRAM[1] (128K BRAM) | PLRAM[2] (128K BRAM) | PLRAM[3] (128K BRAM) |
Approximate available fabric resources in dynamic region | ||||
CLB LUT | 344K | 344K | 344K | 345K |
CLB Register | 702K | 702K | 703K | 703K |
Block RAM Tile | 500 | 500 | 500 | 500 |
URAM | 320 | 320 | 320 | 320 |
DSP | 2877 | 2877 | 2877 | 2877 |
Area | SLR 0 | SLR 1 | SLR 2 |
---|---|---|---|
General information | |||
SLR description | Bottom of device; dedicated to dynamic region. | Middle of device; shared by dynamic and static region resources. | Top of device; dedicated to dynamic region. |
XOCC link syntax for compute unit placement1 | --slr |
--slr |
--slr |
Global memory resources available in dynamic region3 | |||
DDR Memory channels (system port name) | DDR[0] (16 GB DDR4) | DDR[1] (16 GB DDR4, in static region) DDR[2] (16 GB DDR4, in dynamic region) |
DDR[3] (16 GB DDR4) |
PLRAM memory channels (system port name) | PLRAM[0] (128K, BRAM) | PLRAM[1] (128K BRAM) | PLRAM[2] (128K BRAM) |
Approximate available fabric resources in dynamic region | |||
CLB LUT | 354K | 159K | 354K |
CLB Register | 723K | 328K | 723K |
Block RAM Tile | 638 | 326 | 638 |
URAM | 320 | 160 | 320 |
DSP | 2265 | 1317 | 2265 |
Known Issues
Known Issues for theSDAccelandSDxdevelopment environment are available inAR#71729.