Pixel-Wise Multiplication

ThexFmultiplyfunction performs the pixel-wise multiplication between two input images and returns the output image.

Iout(x, y) = Iin1(x, y) * Iin2(x, y) * scale_val

Where:

  • Iout(x, y) is the intensity of the output image at (x, y) position
  • Iin1(x, y) is the intensity of the first input image at (x, y) position
  • Iin2(x, y) is the intensity of the second input image at (x, y) position
  • scale_val is the scale value.

XF_CONVERT_POLICY_TRUNCATE: Results are the least significant bits of the output operand, as if stored in two’s complement binary format in the size of its bit-depth.

XF_CONVERT_POLICY_SATURATE: Results are saturated to the bit depth of the output operand.

API Syntax

template void xFmultiply ( xF::Mat src1, xF::Mat src2, xF::Mat dst, float scale)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 1.xFmultiply Function Parameter Descriptions
Parameter Description
POLICY_TYPE Type of overflow handling. It can be either, XF_CONVERT_POLICY_SATURATE or XF_CONVERT_POLICY_TRUNCATE.
SRC_T pixel type. Options are XF_8UC1 and XF_16SC1.
ROWS Maximum height of input and output image (must be a multiple of 8)
COLS Maximum width of input and output image (must be a multiple of 8)
NPC Number of pixels to be processed per cycle; possible options are XF_NPPC1 and XF_NPPC8 for 1 pixel and 8 pixel operations respectively.
src1 Input image
src2 Input image
dst Output image
scale_val Weighing factor within the range of 0 and 1

Resource Utilization

The following table summarizes the resource utilization in different configurations, generated usingVivado HLS 2017.1tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a grayscale HD (1080x1920) image.

Table 2.xFmultiply Function Resource Utilization Summary
Operating Mode

Operating Frequency

(MHz)

 Utilization Estimate
BRAM_18K DSP_48Es FF LUT CLB
1 pixel 300 0 2 124 59 18
8 pixel 150 0 16 285 108 43

Performance Estimate

The following table summarizes the performance in different configurations, as generated usingVivado HLS 2017.1tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1, to process a grayscale HD (1080x1920) image.

Table 3.xFmultiply Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.6