Resolution Conversion (Resize)

Resolution Conversion is the method used to resize the source image to the size of the destination image. Different types of interpolation techniques can be used in resize function, namely: Nearest-neighbor, Bilinear, and Area interpolation. The type of interpolation can be passed as a template parameter to the API. The following enumeration types can be used to specify the interpolation type:

  • XF_INTERPOLATION_NN - For Nearest-neighbor interpolation
  • XF_INTERPOLATION_BILINEAR - For Bilinear interpolation
  • XF_INTERPOLATION_AREA - For Area interpolation
Note:Scaling factors greater than or equal to 0.25 are supported in down-scaling and values less than or equal to 8 are supported for up-scaling.

API Syntax

template void xFResize (xF::Mat & _src, xF::Mat & _dst)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 1.xFResize Function Parameter Descriptions
Parameter Description
INTERPOLATION_TYPE Interpolation type. The different options possible are
  • XF_INTERPOLATION_NN – Nearest Neighbor Interpolation
  • XF_INTERPOLATION_BILINEAR – Bilinear interpolation
  • XF_INTERPOLATION_AREA – Area Interpolation
TYPE Number of bits per pixel. Only XF_8UC1 is supported.
SRC_ROWS Maximum Height of input image for which the hardware kernel would be built.
SRC_COLS Maximum Width of input image for which the hardware kernel would be built. (must be a multiple of 8).
DST_ROWS Maximum Height of output image for which the hardware kernel would be built.
DST_COLS Maximum Width of output image for which the hardware kernel would be built. (must be a multiple of 8).
NPC Number of pixels to be processed per cycle. Possible options are XF_NPPC1 (1 pixel per cycle) and XF_NPPC8 (8 pixel per cycle)
_src Input Image
_dst Output Image

Resource Utilization

The following table summarizes the resource utilization of Resize function in Resource Optimized (8 pixel) mode and Normal mode, as generated in the Vivado HLS 2017.1 tool for the Xilinx xczu9eg-ffvb1156-2-i-es2 FPGA, to downscale a grayscale HD(1080x1920) image to SD(640x480); and to upscale a HD(1920x1080) image to a 4K(3840x2160) image.

Table 2.xFResize Function Resource Utilization Summary
Operating Mode Utilization Estimate
1 Pixel (at 300 MHz) 8 Pixel (at 150MHz)
LUTs FFs DSPs BRAMs LUTs FFs DSPs BRAMs
Downscale Nearest Neighbor 800 1315 8 4 5079 5720 8 11
Downscale Bilinear 1067 1580 10 7 6511 4863 14 23
Downscale Area 2558 2995 42 30 324991 17726 42 79
Upscale Nearest Neighbor 803 1115 8 8 1599 1636 8 20
Upscale Bilinear 1231 1521 10 15 3588 2662 14 37
Upscale Area 1461 2107 16 25 5861 3611 36 40

Performance Estimate

The following table summarizes the performance estimation of Resize for various configurations, as generated in the Vivado HLS 2017.1 tool for the xczu9eg-ffvb1156-2-i-es2 FPGA at 300 MHz to resize a grayscale image from 1080x1920 to 480x640 (downscale); and to resize a greyscale image from 1080x1920 to 2160x3840 (upscale). This table also shows the latencies obtained for different interpolation types.

Table 3.xFResize Function Performance Estimate Summary
Operating Mode

Operating Frequency

(MHz)

 Latency Estimate (ms)

Downscale

NN

Downscale

Bilinear

Downscale

Area

Upscale

NN

Upscale

Bilinear

Upscale

Area
1 pixel 300 6.94 6.97 7.09 27.71 27.75 27.74