Pyramid Up
The
.The zero padded image is then smoothened using Gaussian image filter. Gaussian filter for the pyramid-up function uses a fixed filter kernel as given below:
xFPyrUp
function is an image up-sampling algorithm. It first inserts zero rows and zero columns after every input row and column making up to the size of the output image. The output image size is always
However, to make up for the pixel intensity that is reduced due to zero padding, each output pixel is multiplied by 4.
API Syntax
template void xFPyrUp (xF::Mat & _src, xF::Mat & _dst)
Parameter Descriptions
The following table describes the template and the function parameters.
Parameter | Description |
---|---|
TYPE | Pixel type. XF_8UC1 is the only supported pixel type. |
ROWS | Maximum Height or number of output rows to build the hardware for this kernel |
COLS | Maximum Width or number of output columns to build the hardware for this kernel |
NPC | Number of pixels to process per cycle. Currently, the kernel supports only 1 pixel per cycle processing (XF_NPPC1). |
_src | Input image stream |
_dst | Output image stream |
Resource Utilization
The following table summarizes the resource utilization of xFPyrUp for 1 pixel per cycle implementation, for a maximum input image size of 1920x1080 pixels. The results are after synthesis inVivado HLS 2017.1for the Xilinx xczu9eg-ffvb1156-1-i-es1 FPGA at 300 MHz.
Operating Mode | Operating Frequency (MHz) |
Utilization Estimate | |||
---|---|---|---|---|---|
LUTs | FFs | DSPs | BRAMs | ||
1 Pixel per Clock Cycle | 300 | 1124 | 1199 | 0 | 10 |
Performance Estimate
The following table summarizes performance estimates of xFPyrUp function onVivado HLS 2017.1for the Xilinx xczu9eg-ffvb1156-1-i-es1 FPGA.
Operating Mode | Operating Frequency (MHz) |
Input Image Size | Latency Estimate |
---|---|---|---|
Max (ms) | |||
1pixel | 300 | 1920x1080 | 27.82 |