Questions and Additional Exercises

To test your understanding, answer the following questions.

  • Why is the number of functions that can be implemented in hardware device-specific?
  • What is the speedup obtained by implementing themmultandmaddkernels in hardware?
  • What sub-tools are invoked by the SDx™ system compiler?
  • Examine the contents of theRelease/_sdsfolder. Notice thereportsfolder. This folder contains multiple log files and report (.rpt) files with detailed logs and reports from all the tools invoked by the build.
  • If you are familiar with Vivado® IP integrator, in the Project Explorer, double-click onRelease/_sds/p0/ipi/zc702.xpr. This is the hardware design generated from the application source code. Open the block diagram and inspect the generated IP blocks.

Answers

  • The amount of programmable logic varies from one device to another. Larger devices allow multiple functions to be implemented in hardware while smaller devices do not.

  • The speedup is about 8 times faster. The application running on the processor takes about 184k cycles while the application running on both the processor and FPGA takes about 22k cycles.

  • sdscc,sds++,xocc,arm-linux-gnueabihf-gcc,arm-linux-gnueabihf-g++,vivado_hls,vivado,bootgen

    • sdsccis used to compile C language sources
    • sds++is used to compile C++ language sources and also to link the object files created bysdsccandsds++
    • xoccis used to compile OpenCL language sources
    • arm-linux-gnueabihf-gccis called bysdsccto generate object code for C language sources that are targeted to the processor
    • arm-linux-gnueabihf-g++is called bysds++to generate object code for C++ language sources that are targeted to the processor, and also to link all the object files to create an executable that runs on the processor
    • vivado_hlsis called bysdscc/sds++to generate RTL code for C/C++ functions that are marked for hardware implementation
    • vivadois called bysds++to generate the bitstream
    • bootgenis called bysds++to create a bootable image containing the executable that runs on the processor along with the bitstream for the PL or FPGA logic portion of the chip