Lab 4: Optimize the Accelerator Using Directives

In this exercise, you modify the source file in the project to observe the effects of Vivado HLS pragmas on the performance of generated hardware. SeeIntroductionfor more information on this topic.

  1. Create a new project in the SDx™ environment (lab4) for theZC702Platform andLinuxSystem Configuration using the design template forMatrix Multiplication and Addition.
  2. Click on the tab labeledlab4to view theSDx Project Settings. If the tab is not visible, in theProject Explorerdouble click on theproject.sdxfile under thelab4project.
  3. In theHW Functionspanel, observe that themaddandmmultfunctions already appear in the list of functions marked for hardware acceleration.
  4. To get the best runtime performance, switch to use theReleaseconfiguration by clicking on the Active Build Configuration option and then selecting Release. You could also selectReleasefrom the Build icon, or by right-clicking the project and selectingBuild Configuration>Set Active>Release. The Release build configuration uses a higher compiler optimization setting than the Debug build configurations.
  5. Double click themmult.cppin the Project Explorer view to bring up the source editor view.
  6. Find the lines where the pragmasHLS pipelineandHLS array_partitionare located.
  7. Remove these pragmas by commenting out the lines.

  8. Save your file.
  9. Right click the top-level folder for the project and clickBuild Projectin the menu.
  10. After the build completes, copy thelab4/Release/sd_cardfolder to an SD card.
  11. Insert the SD card into the ZC702 board and power on the board.
  12. Connect to the board from a serial terminal in the SDx Terminal tab of the SDx IDE. Click the+icon to open the settings.
  13. After the board boots up, you can execute the application at the Linux prompt. Type/mnt/lab4.elf.
    Observe the performance and compare it with the performance achieved with the commented out pragmas present (compare it with the results of lab1). Note that the array_partitionpragmas increase the memory bandwidth for the inner loop by allowing array elements to be read in parallel. The pipeline pragma on the other hand performs pipelining of the loop and allows multiple iterations of a loop to run in parallel.