pragma HLS reset

Description

Adds or removes resets for specific state variables (global or static).

The reset port is used in an FPGA to restore the registers and block RAM connected to the reset port to an initial value any time the reset signal is applied. The presence and behavior of the RTL reset port is controlled using theconfig_rtlconfiguration file. The reset settings include the ability to set the polarity of the reset, and specify whether the reset is synchronous or asynchronous, but more importantly it controls, through the reset option, which registers are reset when the reset signal is applied. SeeClock, Reset, and RTL Outputin theVivado Design Suite User Guide: High-Level Synthesis(UG902) for more information.

Greater control over reset is provided through theRESETpragma. If a variable is a static or global, theRESETpragma is used to explicitly add a reset, or the variable can be removed from the reset by turningoffthe pragma. This can be particularly useful when static or global arrays are present in the design.

Syntax

Place the pragma in the C source within the boundaries of the variable life cycle.

#pragma HLS reset variable=off
Where:

Example 1

This example adds reset to the variable ain function fooeven when the global reset setting is noneor control: 
void foo(int in[3], char a, char b, char c, int out[3]) { #pragma HLS reset variable=a

Example 2

Removes reset from variableain functionfooeven when the global reset setting isstateorall.

void foo(int in[3], char a, char b, char c, int out[3]) { #pragma HLS reset variable=a off

See Also