IP Core

An HDL IP core for a C-callable library must be packaged using the Vivado® tools. This IP core can be located in the Vivado tools IP repository or in any other location. When the library is used, the corresponding IP core is instantiated in the hardware system.

You must package the IP for the Vivado Design Suite as described in theVivado Design Suite User Guide: Designing with IP(UG896). The Vivado IP Packager tool creates a directory structure for the HDL and other source files, and an IP Definition file (component.xml) that conforms to the IEEE-1685 IP-XACT standard. In addition, the packager creates an archive zip file that contains the directory and its contents required by Vivado Design Suite.

The IP can export AXI4, AXI4-Lite, and AXI4 Stream interfaces. The IP control register must exist at address offset 0x0, and can support two different task protocols:
  1. 'none' - in this mode, the control register must be tied to a constant value 0x6. The core then is assumed to run continuously upon power up, with all data synchronized through AXI4 stream interfaces or through asynchronous read or writes to memory-mapped registers via an axilite bus.
  2. 'axilite' - in this mode, the control register must conform to the following specification, which coincides with theaxilitecontrol interface for an IP generated by Vivado HLS.
The control signals are generally self-explanatory. The ap_startsignal initiates the IP execution, ap_doneindicates IP task completion, and ap_readyindicates that the IP is can be started. For more details, see the Vivado HLS documentation for the ap_ctrl_hsbus definition. 
// 0x00 : Control signals // bit 0 - ap_start (Read/Write/COH) // bit 1 - ap_done (Read/COR) // bit 2 - ap_idle (Read) // bit 3 - ap_ready (Read) // bit 7 - auto_restart (Read/Write) // others - reserved // (COR = Clear on Read, COH = Clear on Handshake)
Important:For details on how to integrate HDL IP into the Vivado Design Suite, see Vivado Design Suite User Guide: Creating and Packaging Custom IP( UG1118).