Guide Organization

This guide employs the integrated profiling in SDSoC to analyze and understand which functions would benefit from hardware acceleration and the implications of C/C++ constructs on system performance. The chapters in this guide are organized as follows:

• Chapter 2: What is an SoC?

  This chapter introduces the computational elements available on an FPGA and how they compare to a processor. It covers topics such as FPGA memory hierarchy, logic elements, and how these elements interrelate.

• Chapter 3: Memory Access Optimizations

  This chapter details how the transfer of data between the PS and PL is implemented using datamovers, and how user-specified compiler directives can be used to select specific datamovers optimized for the particular memory architectures, addressing memory allocation, sharing, and cache coherency. The optimizations described in this chapter primarily improve memory accesses, and their effects on the overall design performance are described in detail.

• Chapter 4: Optimizing the Hardware Function

  This chapter describes the compiler directives used to optimized the hardware function and provides a methodology to apply them. These optimizations are primarily targeted to improve data path performance, and their effects on the overall design performance are described in detail.

• Chapter 5: Putting It All Together

  This chapter shows how the steps learned in this guide can be applied to a real-world design example and how existing hardware functions, developed by hardware engineers using Vivado HLS, can be easily incorporated into an SDSoC project. The optimizations used to improve this design target both data path and memory accesses. These optimizations are gradually applied to improve the kernel, and their effects are described in detail.