Performance and Resource Utilization for Video Timing Controller v6.2

Vivado Design Suite Release 2024.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2024.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix-7
artixuplus
Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq-7000
Zynq UltraScale+

Artix-7

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a200t	sbv484	3	artix7_det_gen_waxi_wint_19	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	286	1951	3753	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	sbg484	2	artix7_det_waxi_wint_18	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	265	1492	3113	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a100t	csg324	3	artix7_det_woaxi_wint_17	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	330	300	695	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a100t	csg324	1	artix7_gen_waxi_16	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	221	1032	2793	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a75t	csg324	3	artix7_gen_woaxi_15	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	330	98	131	0	0	0	PRODUCTION 1.23 2018-06-13

artixuplus

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcau25p	ffvb676	1	artixup_det_gen_waxi_wint_24	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	591	2120	3762	0	0	0	PRODUCTION 1.29 05-01-2022
xcau25p	ffvb676	1LV	artixup_det_waxi_wint_23	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	460	1508	3123	0	0	0	PRODUCTION 1.29 05-01-2022
xcau25p	ffvb676	2	artixup_det_woaxi_wint_22	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	825	372	695	0	0	0	PRODUCTION 1.29 05-01-2022
xcau20p	ffvb676	2	artixup_gen_waxi_21	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	766	1056	2799	0	0	0	PRODUCTION 1.29 05-01-2022
xcau20p	ffvb676	1	artixup_gen_woaxi_20	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	913	104	133	0	0	0	PRODUCTION 1.29 05-01-2022

Kintex-7

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	3	kintex7_det_gen_waxi_wint_4	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	429	1982	3757	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbg676	2	kintex7_det_waxi_wint_3	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	424	1498	3113	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	3	kintex7_det_woaxi_wint_2	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	467	351	695	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	2	kintex7_gen_waxi_1	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	429	1052	2793	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	kintex7_gen_woaxi_0	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	385	100	131	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	ffva1156	3	kintexu_det_gen_waxi_wint_9	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	566	2135	3766	0	0	0	PRODUCTION 1.25 12-04-2018
xcku035	fbva676	2	kintexu_det_waxi_wint_8	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	488	1515	3128	0	0	0	PRODUCTION 1.25 12-04-2018
xcku035	fbva676	2	kintexu_det_woaxi_wint_7	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	574	371	695	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	kintexu_gen_waxi_6	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	481	1051	2804	0	0	0	PRODUCTION 1.25 12-04-2018
xcku035	fbva676	3	kintexu_gen_woaxi_5	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	825	103	131	0	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku15p	ffva1156	3	kintexup_det_gen_waxi_wint_14	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	744	2126	3768	0	0	0	PRODUCTION 1.29 05-01-2022
xcku15p	ffva1156	2L	kintexup_det_waxi_wint_13	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	755	1585	3139	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	3	kintexup_det_woaxi_wint_12	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	913	379	695	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	2	kintexup_gen_waxi_11	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	733	1056	2803	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kintexup_gen_woaxi_10	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	836	99	131	0	0	0	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsvd1760	2MP	versal_det_gen_waxi_wint_54	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	644	2335	3698	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	2MP	versal_det_waxi_wint_53	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	707	1897	3058	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	2MP	versal_det_woaxi_wint_52	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	738	536	708	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	3HP	versal_gen_waxi_51	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	825	1173	2581	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	versal_gen_woaxi_50	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	629	180	151	0	0	0	PRODUCTION 2.12 2023-09-01

Virtex-7

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	virtex7_det_gen_waxi_wint_29	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	341	1971	3753	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	virtex7_det_waxi_wint_28	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	330	1494	3109	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	virtex7_det_woaxi_wint_27	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	363	305	695	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	3	virtex7_gen_waxi_26	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	440	1053	2793	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	virtex7_gen_woaxi_25	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	391	99	131	0	0	0	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	3	virtexu_det_gen_waxi_wint_34	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	543	2124	3761	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	virtexu_det_waxi_wint_33	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	582	1587	3126	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	2	virtexu_det_woaxi_wint_32	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	574	371	695	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	2	virtexu_gen_waxi_31	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	613	1052	2804	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	virtexu_gen_woaxi_30	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	543	103	131	0	0	0	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	3	virtexup_det_gen_waxi_wint_39	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	755	2130	3781	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	3	virtexup_det_waxi_wint_38	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	755	1574	3117	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	2	virtexup_det_woaxi_wint_37	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	869	368	695	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	virtexup_gen_waxi_36	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	716	1058	2803	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	virtexup_gen_woaxi_35	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	788	103	131	0	0	0	PRODUCTION 1.28 03-30-2022

Zynq-7000

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7z010	clg225	3	zynq_det_gen_waxi_wint_44	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	281	1947	3752	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z007s	clg400	2	zynq_det_waxi_wint_43	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	265	1490	3117	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z010	clg400	3	zynq_det_woaxi_wint_42	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	341	300	695	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z010	clg400	2	zynq_gen_waxi_41	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	275	1036	2793	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z010	clg400	1	zynq_gen_woaxi_40	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	243	98	131	0	0	0	PRODUCTION 1.12 2019-11-22

Zynq UltraScale+

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu28dr	fsvg1517	2	zynqup_det_gen_waxi_wint_49	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	667	2133	3762	0	0	0	PRODUCTION 1.30 05-03-2022
xczu28dr	fsvg1517	2	zynqup_det_waxi_wint_48	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	672	1578	3117	0	0	0	PRODUCTION 1.30 05-03-2022
xczu28dr	fsvg1517	1	zynqup_det_woaxi_wint_47	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	694	374	695	0	0	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	2	zynqup_gen_waxi_46	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	799	1056	2802	0	0	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zynqup_gen_woaxi_45	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	839	103	132	0	0	0	PRODUCTION 1.30 05-03-2022

COPYRIGHT

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