Performance and Resource Utilization for Video Frame Buffer Read v2.5

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_COLS
MAX_ROWS
MAX_DATA_WIDTH
AXIMM_DATA_WIDTH
HAS_ALPHA
HAS_RGBX8
HAS_YUVX8
HAS_YUYV8
HAS_RGBA8
HAS_YUVA8
HAS_RGBX10
HAS_YUVX10
HAS_Y_UV8
HAS_Y_UV8_420
HAS_RGB8
HAS_YUV8
HAS_Y_UV10
HAS_Y_UV10_420
HAS_Y8
HAS_Y10
HAS_BGRA8
HAS_BGRX8
HAS_UYVY8
HAS_BGR8
HAS_RGBX12
HAS_RGB16
HAS_YUVX12
HAS_Y_UV12
HAS_Y_UV12_420
HAS_Y12
HAS_YUV16
HAS_Y_UV16
HAS_Y_UV16_420
HAS_Y16
HAS_Y_U_V8
HAS_Y_U_V8_420
MAX_NR_PLANES
HAS_Y_U_V10
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_101 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 537 2753 4378 0 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_102 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 537 3107 6137 0 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_103 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 357 4379 9168 0 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_104 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 482 3683 3836 0 14 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_105 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 396 3233 4135 0 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_107 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 435 5402 11628 0 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_108 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 466 7380 13926 0 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_111 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 427 2377 3635 1 11 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_112 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 419 4058 5320 1 14 2 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_113 1 10328 7760 8 64 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 466 3965 5083 2 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_114 2 10328 7760 8 128 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 435 4774 8500 1 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_115 4 10328 7760 8 256 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 ap_clk 482 4534 7652 2 18 2 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_116 8 10328 7760 8 512 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 279 11650 17503 0 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_83 4 10328 7760 8 256 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 381 3525 5760 0 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_85 1 10328 7760 8 64 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 412 2746 4400 0 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_87 4 10328 7760 8 256 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 365 4439 9355 0 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_89 1 10328 7760 8 64 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 396 2502 3566 0 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_90 2 10328 7760 8 128 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 544 3286 6494 0 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_91 4 10328 7760 8 256 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 396 3664 6608 0 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_93 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 396 3404 4551 1 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_94 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 544 1812 2640 1 9 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_96 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 443 10005 20373 1 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_97 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 513 3420 4181 0 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_08bit__conf_98 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 435 1546 2047 0 9 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_08bit__conf_99 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 560 2039 2504 0 11 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_30 2 10328 7760 10 128 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 396 3149 5964 0 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_32 8 10328 7760 10 512 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 607 3352 3727 1 14 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_33 1 10328 7760 10 64 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 435 1484 1819 0 9 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_35 4 10328 7760 10 256 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 404 3471 5416 0 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_36 8 10328 7760 10 512 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 388 5972 8842 1 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_38 2 10328 7760 10 128 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 537 2796 3980 0 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_40 8 10328 7760 10 512 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 435 9761 17869 0 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_42 2 10328 7760 10 128 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 568 2905 4527 0 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_44 8 10328 7760 10 512 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 412 7069 12505 1 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_45 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 404 2723 3700 1 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_46 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 404 3560 6474 1 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_47 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 349 5805 11740 1 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_48 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 341 10062 17703 1 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_50 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 365 3160 5029 1 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_52 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 396 6180 10060 1 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_55 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 552 3831 5926 1 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_56 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 529 5857 8710 0 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_57 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 404 3347 4352 1 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_58 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 568 3538 6466 1 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_59 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 ap_clk 427 6100 12005 1 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_61 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 623 1452 1838 1 8 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_63 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 381 4036 6855 1 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_64 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 ap_clk 450 10660 19404 1 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_65 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 513 3303 4028 0 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_66 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 521 3144 5989 0 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_67 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 412 3756 5874 1 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_68 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 591 3660 3622 1 14 2 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_69 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 521 3534 4703 2 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_70 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 513 4041 7387 1 23 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_71 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 575 2354 3640 1 11 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_10bit__conf_72 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 357 6761 9747 2 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_10bit__conf_76 8 10328 7760 10 512 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 365 11612 19174 3 28 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_12bit__conf_1 1 10328 7760 12 64 0 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 3 0 ap_clk 482 4323 6267 2 25 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_12bit__conf_3 4 10328 7760 12 256 0 1 0 1 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 3 1 ap_clk 373 9223 20562 3 25 3 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_16bit__conf_77 1 10328 7760 16 64 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 3 1 ap_clk 427 5314 9073 2 24 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_16bit__conf_78 2 10328 7760 16 128 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 0 0 3 1 ap_clk 279 6826 14583 2 23 2 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_05 1 10328 7760 8 64 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 466 1441 1814 1 9 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_07 2 10328 7760 8 128 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 623 1473 2148 1 9 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_08 2 10328 7760 10 128 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 615 1471 2084 1 9 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_09 4 10328 7760 8 256 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 458 1795 2776 0 11 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_13 1 10328 7760 8 64 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 631 1414 1822 1 9 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_14 1 10328 7760 10 64 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 443 1460 1834 0 9 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_15 2 10328 7760 8 128 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 458 1504 2104 0 9 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_16 2 10328 7760 10 128 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 458 1500 2104 0 9 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_17 4 10328 7760 8 256 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 638 1617 2737 1 11 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_18 4 10328 7760 10 256 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 458 1805 2667 0 11 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_20 8 10328 7760 10 512 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 575 2425 3972 0 14 2 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 2MP v_frmbuf_rd_alpha__conf_21 1 10328 7760 8 64 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 607 1520 2011 1 9 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_23 2 10328 7760 8 128 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 443 1677 2472 0 9 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP v_frmbuf_rd_alpha__conf_24 2 10328 7760 10 128 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 458 1711 2460 0 9 1 PRODUCTION 2.12 2023-09-01

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_COLS
MAX_ROWS
MAX_DATA_WIDTH
AXIMM_DATA_WIDTH
HAS_ALPHA
HAS_RGBX8
HAS_YUVX8
HAS_YUYV8
HAS_RGBA8
HAS_YUVA8
HAS_RGBX10
HAS_YUVX10
HAS_Y_UV8
HAS_Y_UV8_420
HAS_RGB8
HAS_YUV8
HAS_Y_UV10
HAS_Y_UV10_420
HAS_Y8
HAS_Y10
HAS_BGRA8
HAS_BGRX8
HAS_UYVY8
HAS_BGR8
HAS_RGBX12
HAS_RGB16
HAS_YUVX12
HAS_Y_UV12
HAS_Y_UV12_420
HAS_Y12
HAS_YUV16
HAS_Y_UV16
HAS_Y_UV16_420
HAS_Y16
HAS_Y_U_V8
HAS_Y_U_V8_420
MAX_NR_PLANES
HAS_Y_U_V10
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_100 8 10328 7760 8 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 443 7852 14712 0 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_106 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 435 2743 3762 0 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_109 1 10328 7760 8 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 450 2666 3698 1 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_110 2 10328 7760 8 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 419 2855 4160 1 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_81 1 10328 7760 8 64 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 458 2303 3109 0 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_82 2 10328 7760 8 128 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 623 1662 2120 0 9 0 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_84 8 10328 7760 8 512 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 381 8157 12880 0 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_86 2 10328 7760 8 128 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 435 2721 3762 0 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_88 8 10328 7760 8 512 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 599 3631 3578 0 14 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_92 8 10328 7760 8 512 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 404 5834 8766 0 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_08bit__conf_95 4 10328 7760 8 256 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 412 4421 6976 1 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_29 1 10328 7760 10 64 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 ap_clk 443 2383 3241 1 22 0 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_31 4 10328 7760 10 256 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 0 ap_clk 396 5080 7627 0 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_34 2 10328 7760 10 128 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 568 1637 2008 0 9 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_37 1 10328 7760 10 64 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 ap_clk 435 2317 3168 0 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_39 4 10328 7760 10 256 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 419 5228 7805 1 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_41 1 10328 7760 10 64 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 443 2539 3508 0 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_43 4 10328 7760 10 256 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 ap_clk 560 2482 3361 0 18 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_49 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 458 2656 3698 1 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_51 4 10328 7760 10 256 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 404 5153 8118 1 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_53 1 10328 7760 10 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 412 3028 3839 1 22 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_54 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 ap_clk 396 3924 5610 1 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_60 8 10328 7760 10 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 ap_clk 412 8037 14809 1 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_62 2 10328 7760 10 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 ap_clk 396 3580 5141 1 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_73 1 10328 7760 10 64 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 ap_clk 443 3295 3948 3 15 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_74 2 10328 7760 10 128 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 349 4918 6946 2 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_10bit__conf_75 4 10328 7760 10 256 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 3 1 ap_clk 357 6891 10431 2 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_12bit__conf_2 2 10328 7760 12 128 0 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 0 0 0 1 1 3 0 ap_clk 381 6872 13039 2 23 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_12bit__conf_4 8 10328 7760 12 512 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 599 2363 3725 0 14 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_16bit__conf_79 4 10328 7760 16 256 0 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 3 0 ap_clk 318 11314 26150 2 25 3 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_16bit__conf_80 8 10328 7760 16 512 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 1 3 1 ap_clk 318 19934 42132 3 28 4 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_06 1 10328 7760 10 64 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 623 1450 1861 0 8 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_10 4 10328 7760 10 256 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 623 1850 2646 0 11 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_11 8 10328 7760 8 512 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 552 2259 3656 0 14 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_12 8 10328 7760 10 512 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 568 2295 3661 0 14 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_19 8 10328 7760 8 512 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 607 2331 3711 0 14 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_22 1 10328 7760 10 64 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 568 1518 1870 0 8 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_25 4 10328 7760 8 256 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 568 1914 2823 0 11 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_26 4 10328 7760 10 256 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 591 1949 2899 0 11 1 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_27 8 10328 7760 8 512 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 552 2500 4192 0 14 2 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_frmbuf_rd_alpha__conf_28 8 10328 7760 10 512 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ap_clk 529 2483 4165 0 14 2 PRODUCTION 1.30 05-15-2022

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