Performance and Resource Utilization for 3GPP Turbo Encoder v5.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters											Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Number_Of_Channels	Multiplex_tail_bits	Coding_Rate	External_Ram	BLOCK_SIZE_VALID	ND	RFD	RFD_IN	CE	SCLR	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	1	k7_1_eram_nobsv	1	true	1/3	true	false	false	false	false	false	false	clk	303	603	512	4	1	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_iram_nobsv	1	true	1/3	false	false	false	false	false	false	false	clk	303	606	464	4	1	2	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters											Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Number_Of_Channels	Multiplex_tail_bits	Coding_Rate	External_Ram	BLOCK_SIZE_VALID	ND	RFD	RFD_IN	CE	SCLR	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku025	ffva1156	1	ku_1_eram_nobsv	1	true	1/3	true	false	false	false	false	false	false	clk	385	637	514	4	1	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_iram_nobsv	1	true	1/3	false	false	false	false	false	false	false	clk	369	639	466	4	1	2	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters											Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Number_Of_Channels	Multiplex_tail_bits	Coding_Rate	External_Ram	BLOCK_SIZE_VALID	ND	RFD	RFD_IN	CE	SCLR	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffva1156	1	kup_1_eram_nobsv	1	true	1/3	true	false	false	false	false	false	false	clk	516	637	511	4	1	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_iram_nobsv	1	true	1/3	false	false	false	false	false	false	false	clk	440	635	461	4	1	2	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters											Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Number_Of_Channels	Multiplex_tail_bits	Coding_Rate	External_Ram	BLOCK_SIZE_VALID	ND	RFD	RFD_IN	CE	SCLR	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	ver_1_eram_nobsv	1	true	1/3	true	false	false	false	false	false	false	clk	483	678	519	4	1	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_iram_nobsv	1	true	1/3	false	false	false	false	false	false	false	clk	450	681	475	4	5	0	PRODUCTION 2.12 2023-09-01

Virtex-7

Part Information			Configuration Parameters											Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Number_Of_Channels	Multiplex_tail_bits	Coding_Rate	External_Ram	BLOCK_SIZE_VALID	ND	RFD	RFD_IN	CE	SCLR	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	v7_1_eram_nobsv	1	true	1/3	true	false	false	false	false	false	false	clk	303	603	514	4	1	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_iram_nobsv	1	true	1/3	false	false	false	false	false	false	false	clk	303	607	463	4	1	2	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters											Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Number_Of_Channels	Multiplex_tail_bits	Coding_Rate	External_Ram	BLOCK_SIZE_VALID	ND	RFD	RFD_IN	CE	SCLR	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	1	vu_1_eram_nobsv	1	true	1/3	true	false	false	false	false	false	false	clk	385	634	503	4	1	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_iram_nobsv	1	true	1/3	false	false	false	false	false	false	false	clk	380	652	462	4	1	2	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters											Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Number_Of_Channels	Multiplex_tail_bits	Coding_Rate	External_Ram	BLOCK_SIZE_VALID	ND	RFD	RFD_IN	CE	SCLR	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	vup_1_eram_nobsv	1	true	1/3	true	false	false	false	false	false	false	clk	440	625	511	4	1	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_iram_nobsv	1	true	1/3	false	false	false	false	false	false	false	clk	516	645	466	4	1	2	PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information			Configuration Parameters											Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Number_Of_Channels	Multiplex_tail_bits	Coding_Rate	External_Ram	BLOCK_SIZE_VALID	ND	RFD	RFD_IN	CE	SCLR	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	1LV	zup_1_eram_nobsv	1	true	1/3	true	false	false	false	false	false	false	clk	374	619	530	4	1	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_iram_nobsv	1	true	1/3	false	false	false	false	false	false	false	clk	396	636	489	4	1	2	PRODUCTION 1.30 05-15-2022

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