Performance and Resource Utilization for Soft-Decision FEC v1.1

Vivado Design Suite Release 2024.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2024.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Zynq UltraScale+

Part Information			Configuration Parameters									Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Standard	Turbo_Decode	LDPC_Decode	LDPC_Encode	Parameter_Interface	DIN_Interface	DOUT_Interface	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu21dr	ffvd1156	1LV	zu21dr_dash1LV_decode_5g	5G		true	false	Initialized_retain_I/F	Unconfigured	Unconfigured	core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400 s_axis_din_words_aclk=400 s_axis_dout_words_aclk=400	s_axi_aclk	332	1740	1768	0	7	4	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1LV	zu21dr_dash1LV_decode_Turbo	LTE	true			Initialized			core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400	s_axi_aclk	400	35	21	0	0	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1LV	zu21dr_dash1LV_decode_docsis	DOCSIS_3.1		true	false	Initialized_retain_I/F	Unconfigured	Unconfigured	core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400 s_axis_din_words_aclk=400 s_axis_dout_words_aclk=400	s_axi_aclk	369	507	520	0	1	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1LV	zu21dr_dash1LV_encode_5g	5G		false	true	Initialized_retain_I/F	Unconfigured	Unconfigured	core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400 s_axis_din_words_aclk=400 s_axis_dout_words_aclk=400	s_axi_aclk	319	1696	1685	0	8	2	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zu21dr_dash1_decode_5g	5G		true	false	Initialized_retain_I/F	Unconfigured	Unconfigured	core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400 s_axis_din_words_aclk=400 s_axis_dout_words_aclk=400	s_axi_aclk	400	1748	1768	0	7	4	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zu21dr_dash1_decode_Turbo	LTE	true			Initialized			core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400	s_axi_aclk	400	34	21	0	0	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zu21dr_dash1_decode_docsis	DOCSIS_3.1		true	false	Initialized_retain_I/F	Unconfigured	Unconfigured	core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400 s_axis_din_words_aclk=400 s_axis_dout_words_aclk=400	s_axi_aclk	400	508	520	0	1	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zu21dr_dash1_encode_5g	5G		false	true	Initialized_retain_I/F	Unconfigured	Unconfigured	core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400 s_axis_din_words_aclk=400 s_axis_dout_words_aclk=400	s_axi_aclk	400	1707	1685	0	8	2	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zu21dr_dash2_decode_5g	5G		true	false	Initialized_retain_I/F	Unconfigured	Unconfigured	core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400 s_axis_din_words_aclk=400 s_axis_dout_words_aclk=400	s_axi_aclk	400	1748	1768	0	7	4	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zu21dr_dash2_decode_Turbo	LTE	true			Initialized			core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400	s_axi_aclk	400	34	21	0	0	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zu21dr_dash2_decode_docsis	DOCSIS_3.1		true	false	Initialized_retain_I/F	Unconfigured	Unconfigured	core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400 s_axis_din_words_aclk=400 s_axis_dout_words_aclk=400	s_axi_aclk	400	508	520	0	1	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zu21dr_dash2_encode_5g	5G		false	true	Initialized_retain_I/F	Unconfigured	Unconfigured	core_clk=667 m_axis_dout_aclk=400 m_axis_status_aclk=400 s_axis_ctrl_aclk=400 s_axis_din_aclk=400 s_axis_din_words_aclk=400 s_axis_dout_words_aclk=400	s_axi_aclk	400	1707	1685	0	8	2	PRODUCTION 1.30 05-03-2022

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