Performance and Resource Utilization for Multiplier v12.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	MultType	PortAType	PortAWidth	PortBType	PortBWidth	ConstValue	CcmImp	Multiplier_Construction	OptGoal	Use_Custom_Output_Width	OutputWidthHigh	OutputWidthLow	PipeStages	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	1	k7_1_ccm_28x18	Constant_Coefficient_Multiplier	Signed	28	Signed	18	3069890436404	Block_Memory	Use_LUTs	Area	true	69	0	3	CLK	265	121	68	0	1	5	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_dsp_18x18	Parallel_Multiplier	Signed	18	Signed	18			Use_Mults	Speed		35	0	3	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_dsp_20x20_area	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Area		39	0	3	CLK	544	23	24	1	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_dsp_20x20_speed	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Speed		39	0	4	CLK	544	0	17	2	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_dsp_24x24_area	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Area		47	0	5	CLK	544	152	238	1	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_dsp_24x24_speed	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Speed		47	0	4	CLK	544	0	17	2	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_dsp_25x18	Parallel_Multiplier	Signed	25	Signed	18			Use_Mults	Speed		42	0	3	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_dsp_35x35	Parallel_Multiplier	Signed	35	Signed	35			Use_Mults	Speed		69	0	6	CLK	544	18	69	4	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_dsp_53x53	Parallel_Multiplier	Unsigned	53	Unsigned	53			Use_Mults	Speed		105	0	12	CLK	544	112	263	10	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_lut_12x12_area	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Area		23	0	3	CLK	424	125	173	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_lut_12x12_speed	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Speed		23	0	4	CLK	636	141	189	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_lut_9x9_speed	Parallel_Multiplier	Unsigned	9	Unsigned	9			Use_LUTs	Speed		17	0	4	CLK	636	79	135	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	MultType	PortAType	PortAWidth	PortBType	PortBWidth	ConstValue	CcmImp	Multiplier_Construction	OptGoal	Use_Custom_Output_Width	OutputWidthHigh	OutputWidthLow	PipeStages	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku025	ffva1156	1	ku_1_ccm_28x18	Constant_Coefficient_Multiplier	Signed	28	Signed	18	3069890436404	Block_Memory	Use_LUTs	Area	true	69	0	3	CLK	286	121	68	0	1	5	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_dsp_18x18	Parallel_Multiplier	Signed	18	Signed	18			Use_Mults	Speed		35	0	3	CLK	631	0	0	1	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_dsp_20x20_area	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Area		39	0	3	CLK	631	23	24	1	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_dsp_20x20_speed	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Speed		39	0	4	CLK	631	0	17	2	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_dsp_24x24_area	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Area		47	0	5	CLK	631	152	262	1	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_dsp_24x24_speed	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Speed		47	0	4	CLK	631	0	17	2	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_dsp_25x18	Parallel_Multiplier	Signed	25	Signed	18			Use_Mults	Speed		42	0	3	CLK	631	0	0	1	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_dsp_35x35	Parallel_Multiplier	Signed	35	Signed	35			Use_Mults	Speed		69	0	6	CLK	631	18	69	4	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_dsp_53x53	Parallel_Multiplier	Unsigned	53	Unsigned	53			Use_Mults	Speed		105	0	12	CLK	631	112	277	10	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_lut_12x12_area	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Area		23	0	3	CLK	467	125	173	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_lut_12x12_speed	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Speed		23	0	4	CLK	697	141	189	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_lut_9x9_speed	Parallel_Multiplier	Unsigned	9	Unsigned	9			Use_LUTs	Speed		17	0	4	CLK	713	79	136	0	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	MultType	PortAType	PortAWidth	PortBType	PortBWidth	ConstValue	CcmImp	Multiplier_Construction	OptGoal	Use_Custom_Output_Width	OutputWidthHigh	OutputWidthLow	PipeStages	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffva1156	1	kup_1_ccm_28x18	Constant_Coefficient_Multiplier	Signed	28	Signed	18	3069890436404	Block_Memory	Use_LUTs	Area	true	69	0	3	CLK	440	121	68	0	1	5	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_dsp_18x18	Parallel_Multiplier	Signed	18	Signed	18			Use_Mults	Speed		35	0	3	CLK	866	0	0	1	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_dsp_20x20_area	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Area		39	0	3	CLK	866	23	24	1	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_dsp_20x20_speed	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Speed		39	0	4	CLK	822	0	17	2	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_dsp_24x24_area	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Area		47	0	5	CLK	866	152	238	1	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_dsp_24x24_speed	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Speed		47	0	4	CLK	822	0	17	2	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_dsp_25x18	Parallel_Multiplier	Signed	25	Signed	18			Use_Mults	Speed		42	0	3	CLK	866	0	0	1	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_dsp_35x35	Parallel_Multiplier	Signed	35	Signed	35			Use_Mults	Speed		69	0	6	CLK	822	18	69	4	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_dsp_53x53	Parallel_Multiplier	Unsigned	53	Unsigned	53			Use_Mults	Speed		105	0	12	CLK	817	112	263	10	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_lut_12x12_area	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Area		23	0	3	CLK	713	125	173	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_lut_12x12_speed	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Speed		23	0	4	CLK	872	141	189	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_lut_9x9_speed	Parallel_Multiplier	Unsigned	9	Unsigned	9			Use_LUTs	Speed		17	0	4	CLK	872	79	135	0	0	0	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	MultType	PortAType	PortAWidth	PortBType	PortBWidth	ConstValue	CcmImp	Multiplier_Construction	OptGoal	Use_Custom_Output_Width	OutputWidthHigh	OutputWidthLow	PipeStages	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	ver_1_ccm_28x18	Constant_Coefficient_Multiplier	Signed	28	Signed	18	3069890436404	Block_Memory	Use_LUTs	Area	true	69	0	3	CLK	435	142	256	0	1	5	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_dsp_18x18	Parallel_Multiplier	Signed	18	Signed	18			Use_Mults	Speed		35	0	3	CLK	680	0	0	1	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_dsp_20x20_area	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Area		39	0	3	CLK	680	0	0	1	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_dsp_20x20_speed	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Speed		39	0	4	CLK	680	0	40	1	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_dsp_24x24_area	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Area		47	0	5	CLK	680	1	97	1	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_dsp_24x24_speed	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Speed		47	0	4	CLK	680	0	23	2	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_dsp_25x18	Parallel_Multiplier	Signed	25	Signed	18			Use_Mults	Speed		42	0	3	CLK	680	0	0	1	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_dsp_35x35	Parallel_Multiplier	Signed	35	Signed	35			Use_Mults	Speed		69	0	6	CLK	680	18	139	4	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_dsp_53x53	Parallel_Multiplier	Unsigned	53	Unsigned	53			Use_Mults	Speed		105	0	12	CLK	680	120	462	9	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_lut_12x12_area	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Area		23	0	3	CLK	505	202	180	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_lut_12x12_speed	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Speed		23	0	4	CLK	680	160	189	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	ver_1_lut_9x9_speed	Parallel_Multiplier	Unsigned	9	Unsigned	9			Use_LUTs	Speed		17	0	4	CLK	680	96	136	0	0	0	PRODUCTION 2.12 2023-09-01

Virtex-7

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	MultType	PortAType	PortAWidth	PortBType	PortBWidth	ConstValue	CcmImp	Multiplier_Construction	OptGoal	Use_Custom_Output_Width	OutputWidthHigh	OutputWidthLow	PipeStages	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	v7_1_ccm_28x18	Constant_Coefficient_Multiplier	Signed	28	Signed	18	3069890436404	Block_Memory	Use_LUTs	Area	true	69	0	3	CLK	265	121	68	0	1	5	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_dsp_18x18	Parallel_Multiplier	Signed	18	Signed	18			Use_Mults	Speed		35	0	3	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_dsp_20x20_area	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Area		39	0	3	CLK	544	23	24	1	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_dsp_20x20_speed	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Speed		39	0	4	CLK	544	0	17	2	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_dsp_24x24_area	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Area		47	0	5	CLK	544	152	238	1	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_dsp_24x24_speed	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Speed		47	0	4	CLK	544	0	17	2	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_dsp_25x18	Parallel_Multiplier	Signed	25	Signed	18			Use_Mults	Speed		42	0	3	CLK	544	0	0	1	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_dsp_35x35	Parallel_Multiplier	Signed	35	Signed	35			Use_Mults	Speed		69	0	6	CLK	544	18	69	4	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_dsp_53x53	Parallel_Multiplier	Unsigned	53	Unsigned	53			Use_Mults	Speed		105	0	12	CLK	544	112	263	10	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_lut_12x12_area	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Area		23	0	3	CLK	450	125	173	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_lut_12x12_speed	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Speed		23	0	4	CLK	636	141	189	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_lut_9x9_speed	Parallel_Multiplier	Unsigned	9	Unsigned	9			Use_LUTs	Speed		17	0	4	CLK	636	79	135	0	0	0	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	MultType	PortAType	PortAWidth	PortBType	PortBWidth	ConstValue	CcmImp	Multiplier_Construction	OptGoal	Use_Custom_Output_Width	OutputWidthHigh	OutputWidthLow	PipeStages	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	1	vu_1_ccm_28x18	Constant_Coefficient_Multiplier	Signed	28	Signed	18	3069890436404	Block_Memory	Use_LUTs	Area	true	69	0	3	CLK	281	121	68	0	1	5	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_dsp_18x18	Parallel_Multiplier	Signed	18	Signed	18			Use_Mults	Speed		35	0	3	CLK	631	0	0	1	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_dsp_20x20_area	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Area		39	0	3	CLK	631	23	24	1	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_dsp_20x20_speed	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Speed		39	0	4	CLK	631	0	17	2	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_dsp_24x24_area	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Area		47	0	5	CLK	631	152	238	1	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_dsp_24x24_speed	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Speed		47	0	4	CLK	631	0	17	2	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_dsp_25x18	Parallel_Multiplier	Signed	25	Signed	18			Use_Mults	Speed		42	0	3	CLK	631	0	0	1	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_dsp_35x35	Parallel_Multiplier	Signed	35	Signed	35			Use_Mults	Speed		69	0	6	CLK	631	18	69	4	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_dsp_53x53	Parallel_Multiplier	Unsigned	53	Unsigned	53			Use_Mults	Speed		105	0	12	CLK	631	112	489	10	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_lut_12x12_area	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Area		23	0	3	CLK	478	125	173	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_lut_12x12_speed	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Speed		23	0	4	CLK	702	141	189	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_lut_9x9_speed	Parallel_Multiplier	Unsigned	9	Unsigned	9			Use_LUTs	Speed		17	0	4	CLK	708	79	136	0	0	0	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	MultType	PortAType	PortAWidth	PortBType	PortBWidth	ConstValue	CcmImp	Multiplier_Construction	OptGoal	Use_Custom_Output_Width	OutputWidthHigh	OutputWidthLow	PipeStages	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	vup_1_ccm_28x18	Constant_Coefficient_Multiplier	Signed	28	Signed	18	3069890436404	Block_Memory	Use_LUTs	Area	true	69	0	3	CLK	435	121	68	0	1	5	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_dsp_18x18	Parallel_Multiplier	Signed	18	Signed	18			Use_Mults	Speed		35	0	3	CLK	866	0	0	1	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_dsp_20x20_area	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Area		39	0	3	CLK	866	23	24	1	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_dsp_20x20_speed	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Speed		39	0	4	CLK	822	0	17	2	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_dsp_24x24_area	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Area		47	0	5	CLK	866	152	238	1	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_dsp_24x24_speed	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Speed		47	0	4	CLK	822	0	17	2	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_dsp_25x18	Parallel_Multiplier	Signed	25	Signed	18			Use_Mults	Speed		42	0	3	CLK	866	0	0	1	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_dsp_35x35	Parallel_Multiplier	Signed	35	Signed	35			Use_Mults	Speed		69	0	6	CLK	822	18	69	4	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_dsp_53x53	Parallel_Multiplier	Unsigned	53	Unsigned	53			Use_Mults	Speed		105	0	12	CLK	817	112	363	10	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_lut_12x12_area	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Area		23	0	3	CLK	713	125	173	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_lut_12x12_speed	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Speed		23	0	4	CLK	872	141	189	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_lut_9x9_speed	Parallel_Multiplier	Unsigned	9	Unsigned	9			Use_LUTs	Speed		17	0	4	CLK	872	79	135	0	0	0	PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information			Configuration Parameters														Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	MultType	PortAType	PortAWidth	PortBType	PortBWidth	ConstValue	CcmImp	Multiplier_Construction	OptGoal	Use_Custom_Output_Width	OutputWidthHigh	OutputWidthLow	PipeStages	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	1LV	zup_1_ccm_28x18	Constant_Coefficient_Multiplier	Signed	28	Signed	18	3069890436404	Block_Memory	Use_LUTs	Area	true	69	0	3	CLK	325	121	68	0	1	5	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_dsp_18x18	Parallel_Multiplier	Signed	18	Signed	18			Use_Mults	Speed		35	0	3	CLK	774	0	0	1	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_dsp_20x20_area	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Area		39	0	3	CLK	636	23	44	1	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_dsp_20x20_speed	Parallel_Multiplier	Signed	20	Signed	20			Use_Mults	Speed		39	0	4	CLK	642	0	17	2	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_dsp_24x24_area	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Area		47	0	5	CLK	636	152	279	1	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_dsp_24x24_speed	Parallel_Multiplier	Unsigned	24	Unsigned	24			Use_Mults	Speed		47	0	4	CLK	642	0	17	2	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_dsp_25x18	Parallel_Multiplier	Signed	25	Signed	18			Use_Mults	Speed		42	0	3	CLK	774	0	0	1	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_dsp_35x35	Parallel_Multiplier	Signed	35	Signed	35			Use_Mults	Speed		69	0	6	CLK	636	18	69	4	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_dsp_53x53	Parallel_Multiplier	Unsigned	53	Unsigned	53			Use_Mults	Speed		105	0	12	CLK	636	112	418	10	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_lut_12x12_area	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Area		23	0	3	CLK	538	125	173	0	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_lut_12x12_speed	Parallel_Multiplier	Unsigned	12	Unsigned	12			Use_LUTs	Speed		23	0	4	CLK	636	141	189	0	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_lut_9x9_speed	Parallel_Multiplier	Unsigned	9	Unsigned	9			Use_LUTs	Speed		17	0	4	CLK	636	79	135	0	0	0	PRODUCTION 1.30 05-15-2022

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Copyright 2023 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

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