Resource Utilization for ILA (Integrated Logic Analyzer) v6.0

Vivado Design Suite Release 2015.3

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

• Resource figures are taken from the utilization report issued at the end of implementation in Vivado Design Suite.
The frequencies used for clock inputs are stated for each test case.
• LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
• Default Vivado Design Suite 2015.3 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

• Kintex-7
• Virtex UltraScale

Kintex-7

Virtex UltraScale

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