Resource Utilization for IBERT Ultrascale GTH v1.3

Vivado Design Suite Release 2017.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2017.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Kintex UltraScale

Part Information			Configuration Parameters																																																																Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_ENABLE_DIFF_TERM	C_NUM_QUADS	C_SYSCLK_FREQUENCY	C_SYSCLK_IO_PIN_LOC_N	C_SYSCLK_IO_PIN_LOC_P	C_SYSCLK_IS_DIFF	C_DISABLE_SYSCLK_BUF	C_SYSCLK_IO_PIN_STD	C_SYSCLK_MODE_EXTERNAL	C_SYSCLOCK_SOURCE_INT	C_RXOUTCLK_FREQUENCY	C_RXOUTCLK_N_PIN_LOCATION	C_RXOUTCLK_PIN_LOCATION	C_RXOUTCLK_IS_DIFF	C_RXOUTCLK_PIN_STD	C_RXOUTCLK_GT_LOCATION	C_ADD_RXOUTCLK_PROBES	C_REFCLK_SOURCE_QUAD_17	C_REFCLK_SOURCE_QUAD_16	C_REFCLK_SOURCE_QUAD_15	C_REFCLK_SOURCE_QUAD_14	C_REFCLK_SOURCE_QUAD_13	C_REFCLK_SOURCE_QUAD_12	C_REFCLK_SOURCE_QUAD_11	C_REFCLK_SOURCE_QUAD_10	C_REFCLK_SOURCE_QUAD_9	C_REFCLK_SOURCE_QUAD_8	C_REFCLK_SOURCE_QUAD_7	C_REFCLK_SOURCE_QUAD_6	C_REFCLK_SOURCE_QUAD_5	C_REFCLK_SOURCE_QUAD_4	C_REFCLK_SOURCE_QUAD_3	C_REFCLK_SOURCE_QUAD_2	C_REFCLK_SOURCE_QUAD_1	C_REFCLK_SOURCE_QUAD_0	C_PROTOCOL_QUAD17	C_PROTOCOL_QUAD16	C_PROTOCOL_QUAD15	C_PROTOCOL_QUAD14	C_PROTOCOL_QUAD13	C_PROTOCOL_QUAD12	C_PROTOCOL_QUAD11	C_PROTOCOL_QUAD10	C_PROTOCOL_QUAD9	C_PROTOCOL_QUAD8	C_PROTOCOL_QUAD7	C_PROTOCOL_QUAD6	C_PROTOCOL_QUAD5	C_PROTOCOL_QUAD4	C_PROTOCOL_QUAD3	C_PROTOCOL_QUAD2	C_PROTOCOL_QUAD1	C_PROTOCOL_QUAD0	C_CHECK_REFCLK_SOURCES	C_PROTOCOL_PLL_3	C_PROTOCOL_PLL_2	C_PROTOCOL_PLL_1	C_PROTOCOL_QUAD_COUNT_3	C_PROTOCOL_QUAD_COUNT_2	C_PROTOCOL_QUAD_COUNT_1	C_PROTOCOL_REFCLK_FREQUENCY_3	C_PROTOCOL_REFCLK_FREQUENCY_2	C_PROTOCOL_REFCLK_FREQUENCY_1	C_PROTOCOL_DATAWIDTH_3	C_PROTOCOL_DATAWIDTH_2	C_PROTOCOL_DATAWIDTH_1	C_PROTOCOL_MAXLINERATE_3	C_PROTOCOL_MAXLINERATE_2	C_PROTOCOL_MAXLINERATE_1	C_PROTOCOL_3	C_PROTOCOL_2	C_PROTOCOL_1	C_PROTOCOL_COUNT	Fixed clocks (MHz)	LUTs	FFs	LUT-FF Pairs	DSP48s	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	ffva1156	-3	ibert	true	1	300	AK16	AK17	1	1	DIFF_SSTL15	1	External	125.0	UNASSIGNED	UNASSIGNED	1	LVCMOS25	QUAD227_0	FALSE	None	None	None	None	None	None	None	None	None	None	None	None	None	None	MGTREFCLK0_227	None	None	None	None	None	None	None	None	None	None	None	None	None	None	None	None	None	Custom_1_/_5_Gbps	None	None	None	1	QPLL0	QPLL0	QPLL0	0	0	1	100	100	156.25	40	40	40	5	5	5	Custom_3	Custom_2	Custom_1	1	DUT/inst/QUAD[0].u_q/CH[0].u_ch/u_gthe3_channel/DMONITOROUT[16]=250 DUT/inst/QUAD[0].u_q/CH[1].u_ch/u_gthe3_channel/DMONITOROUT[16]=250 DUT/inst/QUAD[0].u_q/CH[2].u_ch/u_gthe3_channel/DMONITOROUT[16]=250 DUT/inst/QUAD[0].u_q/CH[3].u_ch/u_gthe3_channel/DMONITOROUT[16]=250 clk=300	7529	14505	3143	8	20	0	PRODUCTION 1.23 03-22-2017

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