Resource Utilization for IBERT 7 Series GTZ v3.1

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

The IP core's example design is opened in Vivado Design Suite, and synthesis and implementation are run. Resource figures are taken from the utilization report issued at the end of implementation, and are for the IP instance only, excluding other parts of the example design.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2019.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Virtex-7

Part Information			Configuration Parameters																																																									Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_RXOUTCLK_IO_PIN_LOC_N	C_RXOUTCLK_IO_PIN_LOC_P	C_RXOUTCLK_IO_PIN_STD	C_ADD_RXOUTCLK_PROBES	C_PROTOCOL_COUNT	C_SYSCLK_IO_PIN_LOC_N	C_SYSCLK_IO_PIN_LOC_P	C_SYSCLK_IO_PIN_STD	C_SYSCLK_FREQUENCY	C_PD_MGT15	C_PD_MGT14	C_PD_MGT13	C_PD_MGT12	C_PD_MGT11	C_PD_MGT10	C_PD_MGT9	C_PD_MGT8	C_PD_MGT7	C_PD_MGT6	C_PD_MGT5	C_PD_MGT4	C_PD_MGT3	C_PD_MGT2	C_PD_MGT1	C_PD_MGT0	C_PROTOCOL_MGT15	C_PROTOCOL_MGT14	C_PROTOCOL_MGT13	C_PROTOCOL_MGT12	C_PROTOCOL_MGT11	C_PROTOCOL_MGT10	C_PROTOCOL_MGT9	C_PROTOCOL_MGT8	C_PROTOCOL_MGT7	C_PROTOCOL_MGT6	C_PROTOCOL_MGT5	C_PROTOCOL_MGT4	C_PROTOCOL_MGT3	C_PROTOCOL_MGT2	C_PROTOCOL_MGT1	C_PROTOCOL_MGT0	C_SYSCLK_MODE_EXTERNAL	C_PROTOCOL0	C_PROTOCOL1	C_LINERATE1	C_LINERATE0	C_DATAWIDTH0	C_DATAWIDTH1	C_REFCLK0	C_REFCLK1	C_LANECOUNT0	C_LANECOUNT1	C_REFCLK_SOURCE0	C_REFCLK_SOURCE1	C_RXOUTCLK_SOURCE_LANE	C_SYSCLK_REFCLK_SOURCE	LUTs	FFs	DSP48s	36k BRAMs	18k BRAMs	Speedfile Status
xc7vh580t	hcg1155	-2	ibert_7series_gtz_v3_1_0	UNCONSTRAINED	UNCONSTRAINED	BLVDS_25	false	1	AL25	AL24	DIFF_SSTL15	200.0	false	false	false	false	false	false	false	false	false	false	false	false	false	false	false	false	None	None	None	None	None	None	None	None	Protocol0/10.3125	Protocol0/10.3125	Protocol0/10.3125	Protocol0/10.3125	Protocol0/10.3125	Protocol0/10.3125	Protocol0/10.3125	Protocol0/10.3125	true	Protocol0	Protocol1	10.3125	10.3125	160	160	322.26563	322.26563	8	0	REFCLK0	REFCLK0	LANE0	LANE0	20685	31595	0	0	0	PRODUCTION 1.08 2014-09-11
xc7vh580t	hcg1155	-2	ibert_7series_gtz_v3_1_6	UNCONSTRAINED	UNCONSTRAINED	BLVDS_25	false	1	AL25	AL24	DIFF_SSTL15	200.0	false	false	false	false	false	false	false	false	false	false	false	false	false	false	false	false	None	None	None	None	None	None	None	None	Protocol0/28.05	Protocol0/28.05	Protocol0/28.05	Protocol0/28.05	Protocol0/28.05	Protocol0/28.05	Protocol0/28.05	Protocol0/28.05	true	Protocol0	Protocol1	10.3125	28.05	160	160	425	322.26563	8	0	REFCLK0	REFCLK0	LANE0	LANE0	20703	31595	0	0	0	PRODUCTION 1.08 2014-09-11

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