Resource Utilization for IBERT 7 Series GTP v3.0

Vivado Design Suite Release 2017.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2017.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Artix-7

Part Information			Configuration Parameters																																																									Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_ENABLE_DIFF_TERM	C_SYSCLK_FREQUENCY	C_SYSCLK_IO_PIN_LOC_N	C_SYSCLK_IO_PIN_LOC_P	C_SYSCLK_IS_DIFF	C_DISABLE_SYSCLK_BUF	C_SYSCLK_IO_PIN_STD	C_SYSCLK_MODE_EXTERNAL	C_SYSCLOCK_SOURCE_INT	C_RXOUTCLK_FREQUENCY	C_RXOUTCLK_N_PIN_LOCATION	C_RXOUTCLK_PIN_LOCATION	C_RXOUTCLK_IS_DIFF	C_RXOUTCLK_PIN_STD	C_RXOUTCLK_GT_LOCATION	C_ADD_RXOUTCLK_PROBES	C_CHANNEL_QUAD_3	C_CHANNEL_QUAD_2	C_CHANNEL_QUAD_1	C_CHANNEL_QUAD_0	C_REFCLK_SOURCE_QUAD_3	C_REFCLK_SOURCE_QUAD_2	C_REFCLK_SOURCE_QUAD_1	C_REFCLK_SOURCE_QUAD_0	C_PROTOCOL_QUAD3	C_PROTOCOL_QUAD2	C_PROTOCOL_QUAD1	C_PROTOCOL_QUAD0	C_GT_CORRECT	C_CHECK_REFCLK_SOURCES	C_PROTOCOL_RXREFCLK_FREQUENCY_3	C_PROTOCOL_RXREFCLK_FREQUENCY_2	C_PROTOCOL_RXREFCLK_FREQUENCY_1	C_PROTOCOL_GT_COUNT_3	C_PROTOCOL_GT_COUNT_2	C_PROTOCOL_GT_COUNT_1	C_PROTOCOL_MAXLINERATE_3	C_PROTOCOL_MAXLINERATE_2	C_PROTOCOL_MAXLINERATE_1	C_PROTOCOL_DATAWIDTH_3	C_PROTOCOL_DATAWIDTH_2	C_PROTOCOL_DATAWIDTH_1	C_PROTOCOL_3	C_PROTOCOL_2	C_PROTOCOL_1	C_PROTOCOL_USE_PLL1_3	C_PROTOCOL_USE_PLL1_2	C_PROTOCOL_USE_PLL1_1	C_PROTOCOL_USE_QUAD_PLL_1	C_PROTOCOL_USE_QUAD_PLL_2	C_PROTOCOL_USE_QUAD_PLL_3	C_PROTOCOL_USE_PLL0_3	C_PROTOCOL_USE_PLL0_2	C_PROTOCOL_USE_PLL0_1	C_PROTOCOL_COUNT	C_SI_VER	LUTs	FFs	LUT-FF Pairs	DSP48s	36k BRAMs	18k BRAMs	Speedfile Status
xc7a200t	fbg676	-3	ibert_7s_gtp_v3_0_daily1048509_0	false	312.500	P3	R3	1	1	DIFF_SSTL15	1	External	195.3125	N4	P4	1	DIFF_SSTL15	QUAD_213	true	Channel_0	Channel_0	Channel_0	Channel_0	None	None	None	MGTREFCLK1_213	None	None	None	Custom_1_/_3.125_Gbps	1	1	125.000	125.000	312.500	0	0	1	3.125	3.125	3.125	16	16	16	Custom_3	Custom_2	Custom_1	true	true	true	PLL1	PLL0	PLL0	true	true	true	1	General_ES/Production	4312	9634	1522	8	0	0	PRODUCTION 1.16 2016-11-09

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