Performance and Resource Utilization for I2S Receiver v1.0

Vivado Design Suite Release 2024.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2024.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Virtex-7
Zynq UltraScale+

Virtex-7

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_NUM_CHANNELS	C_DWIDTH	C_DEPTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	test_v7_wMASTER_w2CH_w16DW_1024Depth	2	16	1024	m_axis_aud_aclk=100 s_axi_ctrl_aclk=100	aud_mclk	313	512	1728	0	1	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	test_v7_wMASTER_w2CH_w16DW_64Depth	2	16	64	m_axis_aud_aclk=100 s_axi_ctrl_aclk=100	aud_mclk	313	490	1675	0	0	1	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	test_v7_wMASTER_w2CH_w24DW_1024Depth	2	24	1024	m_axis_aud_aclk=100 s_axi_ctrl_aclk=100	aud_mclk	325	539	1776	0	1	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	test_v7_wMASTER_w8CH_w24DW_1024Depth	8	24	1024	m_axis_aud_aclk=100 s_axi_ctrl_aclk=100	aud_mclk	313	1042	2202	0	1	0	PRODUCTION 1.12 2014-09-11

Zynq UltraScale+

Part Information			Configuration Parameters					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_NUM_CHANNELS	C_DWIDTH	C_DEPTH	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	2	test_zuplus_wMASTER_w2CH_w16DW_1024Depth	2	16	1024	m_axis_aud_aclk=100 s_axi_ctrl_aclk=100	aud_mclk	713	515	1726	0	1	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	2	test_zuplus_wMASTER_w2CH_w16DW_64Depth	2	16	64	m_axis_aud_aclk=100 s_axi_ctrl_aclk=100	aud_mclk	725	471	1674	0	0	1	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	2	test_zuplus_wMASTER_w2CH_w24DW_1024Depth	2	24	1024	m_axis_aud_aclk=100 s_axi_ctrl_aclk=100	aud_mclk	738	542	1774	0	1	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	2	test_zuplus_wMASTER_w8CH_w24DW_1024Depth	8	24	1024	m_axis_aud_aclk=100 s_axi_ctrl_aclk=100	aud_mclk	738	1052	2200	0	1	0	PRODUCTION 1.30 05-15-2022

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