Resource Utilization for Gmii to Rgmii v4.0

Vivado Design Suite Release 2017.4

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Zynq-7000

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_EXTERNAL_CLOCK
RGMII_TXC_SKEW
SupportLevel
LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs BUFGCTRL BUFG BUFR MMCME2_ADV Speedfile Status
xc7z045 ffg900 -2 a_z7_exc_sk0_s true 0 Include_Shared_Logic_in_Core 62 135 39 0 0 0 2 2 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 ffg900 -2 a_z7_exc_sk1_s true 1 Include_Shared_Logic_in_Core 62 135 39 0 0 0 2 2 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 ffg900 -2 a_z7_nexc_sk0_s false 0 Include_Shared_Logic_in_Core 63 135 42 0 0 0 4 2 1 1 PRODUCTION 1.11 2014-09-11
xc7z045 ffg900 -2 a_z7_nexc_sk1_s false 1 Include_Shared_Logic_in_Core 63 135 41 0 0 0 4 2 1 1 PRODUCTION 1.11 2014-09-11
xc7z045 ffg900 -2 a_z7_nexc_sk2_s false 2 Include_Shared_Logic_in_Core 63 141 40 0 0 0 6 2 2 1 PRODUCTION 1.11 2014-09-11
xc7z045 ffg900 -2 b_z7_exc_sk0_ns true 0 Include_Shared_Logic_in_Example_Design 57 114 38 0 0 0 1 1 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 ffg900 -2 b_z7_exc_sk1_ns true 1 Include_Shared_Logic_in_Example_Design 57 114 38 0 0 0 1 1 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 ffg900 -2 b_z7_nexc_sk0_ns false 0 Include_Shared_Logic_in_Example_Design 57 114 35 0 0 0 3 1 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 ffg900 -2 b_z7_nexc_sk1_ns false 1 Include_Shared_Logic_in_Example_Design 58 114 36 0 0 0 3 1 0 0 PRODUCTION 1.11 2014-09-11
xc7z045 ffg900 -2 b_z7_nexc_sk2_ns false 2 Include_Shared_Logic_in_Example_Design 59 120 36 0 0 0 5 1 0 0 PRODUCTION 1.11 2014-09-11

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_EXTERNAL_CLOCK
RGMII_TXC_SKEW
SupportLevel
LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs BUFGCE BUFGCE_DIV Speedfile Status
xczu2eg sbva484 -2 c_zup_exc_sk0_s true 0 Include_Shared_Logic_in_Core 61 135 34 0 0 0 2 0 PRODUCTION 1.16 10-25-2017
xczu2eg sbva484 -2 c_zup_exc_sk1_s true 1 Include_Shared_Logic_in_Core 63 135 40 0 0 0 2 0 PRODUCTION 1.16 10-25-2017
xczu2eg sbva484 -2 c_zup_nexc_sk0_s false 0 Include_Shared_Logic_in_Core 61 135 38 0 0 0 2 1 PRODUCTION 1.16 10-25-2017
xczu2eg sbva484 -2 c_zup_nexc_sk1_s false 1 Include_Shared_Logic_in_Core 61 135 36 0 0 0 2 1 PRODUCTION 1.16 10-25-2017
xczu2eg sbva484 -2 c_zup_nexc_sk2_s false 2 Include_Shared_Logic_in_Core 62 141 32 0 0 0 2 2 PRODUCTION 1.16 10-25-2017
xczu2eg sbva484 -2 d_zup_exc_sk0_ns true 0 Include_Shared_Logic_in_Example_Design 52 114 32 0 0 0 1 0 PRODUCTION 1.16 10-25-2017
xczu2eg sbva484 -2 d_zup_exc_sk1_ns true 1 Include_Shared_Logic_in_Example_Design 51 114 30 0 0 0 1 0 PRODUCTION 1.16 10-25-2017
xczu2eg sbva484 -2 d_zup_nexc_sk0_ns false 0 Include_Shared_Logic_in_Example_Design 55 114 34 0 0 0 1 0 PRODUCTION 1.16 10-25-2017
xczu2eg sbva484 -2 d_zup_nexc_sk1_ns false 1 Include_Shared_Logic_in_Example_Design 53 114 30 0 0 0 1 0 PRODUCTION 1.16 10-25-2017
xczu2eg sbva484 -2 d_zup_nexc_sk2_ns false 2 Include_Shared_Logic_in_Example_Design 55 120 31 0 0 0 1 0 PRODUCTION 1.16 10-25-2017

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