Performance and Resource Utilization for Discrete Fourier Transform v4.2

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_d16_area_1536 16 Area false true CLK 347 3648 4782 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_area_5g 16 Area false true true CLK 166 3741 4842 16 10 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_area_no1536 16 Area false false CLK 341 3634 4716 16 3 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_spd_1536 16 Speed false true CLK 347 3648 4782 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_spd_5g 16 Speed false true true CLK 166 3741 4842 16 10 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d16_spd_no1536 16 Speed false false CLK 341 3634 4716 16 3 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d8_area_1536 8 Area false true CLK 347 2908 3579 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d8_area_5g 8 Area false true true CLK 166 3099 3764 16 10 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_d8_area_no1536 8 Area false false CLK 347 2917 3533 16 3 4 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_d16_area_1536 16 Area false true CLK 407 3541 4691 16 4 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_area_5g 16 Area false true true CLK 402 3844 4947 16 10 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_area_no1536 16 Area false false CLK 407 3544 4836 16 3 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_spd_1536 16 Speed false true CLK 407 3541 4691 16 4 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_spd_5g 16 Speed false true true CLK 402 3844 4947 16 10 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d16_spd_no1536 16 Speed false false CLK 407 3544 4836 16 3 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d8_area_1536 8 Area false true CLK 402 2883 3756 16 4 4 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d8_area_5g 8 Area false true true CLK 402 3186 3803 16 10 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_d8_area_no1536 8 Area false false CLK 407 2909 3567 16 3 4 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_d16_area_1536 16 Area false true CLK 566 3836 5032 16 4 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_area_5g 16 Area false true true CLK 566 4154 5112 16 10 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_area_no1536 16 Area false false CLK 566 3841 4987 16 3 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_spd_1536 16 Speed false true CLK 566 3836 5032 16 4 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_spd_5g 16 Speed false true true CLK 566 4154 5112 16 10 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d16_spd_no1536 16 Speed false false CLK 566 3841 4987 16 3 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d8_area_1536 8 Area false true CLK 555 3080 3795 16 4 4 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d8_area_5g 8 Area false true true CLK 555 3359 4079 16 10 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_d8_area_no1536 8 Area false false CLK 571 3147 3676 16 3 4 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_d16_area_1536 16 Area false true CLK 461 3521 5008 16 4 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_d16_area_5g 16 Area false true true CLK 472 3948 5036 16 10 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_d16_area_no1536 16 Area false false CLK 461 3522 5150 16 3 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_d16_spd_1536 16 Speed false true CLK 461 3521 5008 16 4 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_d16_spd_5g 16 Speed false true true CLK 472 3948 5036 16 10 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_d16_spd_no1536 16 Speed false false CLK 461 3522 5150 16 3 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_d8_area_1536 8 Area false true CLK 467 2941 3891 16 4 4 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_d8_area_5g 8 Area false true true CLK 456 3223 3953 16 10 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_d8_area_no1536 8 Area false false CLK 450 2880 3827 16 3 4 PRODUCTION 2.12 2023-09-01

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_d16_area_1536 16 Area false true CLK 341 3627 4672 16 4 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_area_5g 16 Area false true true CLK 166 3743 4842 16 10 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_area_no1536 16 Area false false CLK 347 3638 4737 16 3 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_spd_1536 16 Speed false true CLK 341 3627 4672 16 4 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_spd_5g 16 Speed false true true CLK 166 3743 4842 16 10 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d16_spd_no1536 16 Speed false false CLK 347 3638 4737 16 3 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d8_area_1536 8 Area false true CLK 347 2901 3550 16 4 4 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d8_area_5g 8 Area false true true CLK 161 3095 3764 16 10 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_d8_area_no1536 8 Area false false CLK 341 2903 3541 16 3 4 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_d16_area_1536 16 Area false true CLK 407 3554 4919 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_area_5g 16 Area false true true CLK 396 3855 4938 16 10 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_area_no1536 16 Area false false CLK 407 3558 4837 16 3 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_spd_1536 16 Speed false true CLK 407 3554 4919 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_spd_5g 16 Speed false true true CLK 396 3855 4938 16 10 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d16_spd_no1536 16 Speed false false CLK 407 3558 4837 16 3 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d8_area_1536 8 Area false true CLK 396 2876 3701 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d8_area_5g 8 Area false true true CLK 396 3180 3889 16 10 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_d8_area_no1536 8 Area false false CLK 407 2904 3571 16 3 4 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_d16_area_1536 16 Area false true CLK 566 3883 5106 16 4 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_area_5g 16 Area false true true CLK 566 4187 5187 16 10 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_area_no1536 16 Area false false CLK 560 3882 4963 16 3 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_spd_1536 16 Speed false true CLK 566 3883 5106 16 4 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_spd_5g 16 Speed false true true CLK 566 4187 5187 16 10 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d16_spd_no1536 16 Speed false false CLK 560 3882 4963 16 3 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d8_area_1536 8 Area false true CLK 571 3137 3815 16 4 4 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d8_area_5g 8 Area false true true CLK 555 3358 4016 16 10 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_d8_area_no1536 8 Area false false CLK 566 3157 3719 16 3 4 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_5G
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_d16_area_1536 16 Area false true CLK 456 3636 5024 16 4 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_area_5g 16 Area false true true CLK 456 3936 5125 16 10 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_area_no1536 16 Area false false CLK 456 3659 5025 16 3 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_spd_1536 16 Speed false true CLK 456 3636 5024 16 4 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_spd_5g 16 Speed false true true CLK 456 3936 5125 16 10 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d16_spd_no1536 16 Speed false false CLK 456 3659 5025 16 3 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d8_area_1536 8 Area false true CLK 456 2894 3902 16 4 4 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d8_area_5g 8 Area false true true CLK 456 3235 4120 16 10 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_d8_area_no1536 8 Area false false CLK 456 2894 3872 16 3 4 PRODUCTION 1.30 05-15-2022

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