Performance and Resource Utilization for Discrete Fourier Transform v4.2

Vivado Design Suite Release 2022.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command:set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2022.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq UltraScale+

Kintex-7

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	1	k7_1_d16_area_1536	16	Area	false		true	CLK	330	3603	4901	16	4	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_area_5g	16	Area	false	true	true	CLK	166	3750	4842	16	10	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_area_no1536	16	Area	false		false	CLK	341	3640	4698	16	3	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_spd_1536	16	Speed	false		true	CLK	330	3603	4901	16	4	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_spd_5g	16	Speed	false	true	true	CLK	166	3750	4842	16	10	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d16_spd_no1536	16	Speed	false		false	CLK	341	3640	4698	16	3	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d8_area_1536	8	Area	false		true	CLK	341	2896	3526	16	4	4	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d8_area_5g	8	Area	false	true	true	CLK	161	3094	3764	16	10	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	k7_1_d8_area_no1536	8	Area	false		false	CLK	352	2905	3623	16	3	4	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku025	ffva1156	1	ku_1_d16_area_1536	16	Area	false		true	CLK	402	3549	4797	16	4	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_area_5g	16	Area	false	true	true	CLK	396	3826	4882	16	10	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_area_no1536	16	Area	false		false	CLK	407	3548	4632	16	3	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_spd_1536	16	Speed	false		true	CLK	402	3549	4797	16	4	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_spd_5g	16	Speed	false	true	true	CLK	396	3826	4882	16	10	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d16_spd_no1536	16	Speed	false		false	CLK	407	3548	4632	16	3	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d8_area_1536	8	Area	false		true	CLK	407	2893	3558	16	4	4	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d8_area_5g	8	Area	false	true	true	CLK	396	3187	3879	16	10	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	ku_1_d8_area_no1536	8	Area	false		false	CLK	407	2900	3542	16	3	4	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku11p	ffva1156	1	kup_1_d16_area_1536	16	Area	false		true	CLK	566	3854	4967	16	4	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_area_5g	16	Area	false	true	true	CLK	566	4120	5198	16	10	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_area_no1536	16	Area	false		false	CLK	555	3831	5055	16	3	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_spd_1536	16	Speed	false		true	CLK	566	3854	4967	16	4	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_spd_5g	16	Speed	false	true	true	CLK	566	4120	5198	16	10	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d16_spd_no1536	16	Speed	false		false	CLK	555	3831	5055	16	3	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d8_area_1536	8	Area	false		true	CLK	566	3106	3706	16	4	4	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d8_area_5g	8	Area	false	true	true	CLK	566	3406	4054	16	10	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kup_1_d8_area_no1536	8	Area	false		false	CLK	555	3084	3627	16	3	4	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	ver_1_d16_area_1536	16	Area	false		true	CLK	450	3490	5034	16	4	4	PRODUCTION 2.10 2022-05-19
xcvc1902	vsva2197	1LP	ver_1_d16_area_5g	16	Area	false	true	true	CLK	456	3894	5262	16	10	0	PRODUCTION 2.10 2022-05-19
xcvc1902	vsva2197	1LP	ver_1_d16_area_no1536	16	Area	false		false	CLK	456	3499	5007	16	3	4	PRODUCTION 2.10 2022-05-19
xcvc1902	vsva2197	1LP	ver_1_d16_spd_1536	16	Speed	false		true	CLK	450	3490	5034	16	4	4	PRODUCTION 2.10 2022-05-19
xcvc1902	vsva2197	1LP	ver_1_d16_spd_5g	16	Speed	false	true	true	CLK	456	3894	5262	16	10	0	PRODUCTION 2.10 2022-05-19
xcvc1902	vsva2197	1LP	ver_1_d16_spd_no1536	16	Speed	false		false	CLK	456	3499	5007	16	3	4	PRODUCTION 2.10 2022-05-19
xcvc1902	vsva2197	1LP	ver_1_d8_area_1536	8	Area	false		true	CLK	456	2841	3838	16	4	4	PRODUCTION 2.10 2022-05-19
xcvc1902	vsva2197	1LP	ver_1_d8_area_5g	8	Area	false	true	true	CLK	450	3215	4112	16	10	0	PRODUCTION 2.10 2022-05-19
xcvc1902	vsva2197	1LP	ver_1_d8_area_no1536	8	Area	false		false	CLK	456	2864	3874	16	3	4	PRODUCTION 2.10 2022-05-19

Virtex-7

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	v7_1_d16_area_1536	16	Area	false		true	CLK	347	3635	4643	16	4	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_area_5g	16	Area	false	true	true	CLK	177	3755	4842	16	10	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_area_no1536	16	Area	false		false	CLK	325	3601	4640	16	3	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_spd_1536	16	Speed	false		true	CLK	347	3635	4643	16	4	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_spd_5g	16	Speed	false	true	true	CLK	177	3755	4842	16	10	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d16_spd_no1536	16	Speed	false		false	CLK	325	3601	4640	16	3	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d8_area_1536	8	Area	false		true	CLK	347	2896	3595	16	4	4	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d8_area_5g	8	Area	false	true	true	CLK	166	3096	3764	16	10	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	v7_1_d8_area_no1536	8	Area	false		false	CLK	347	2903	3531	16	3	4	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	1	vu_1_d16_area_1536	16	Area	false		true	CLK	402	3566	4944	16	4	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_area_5g	16	Area	false	true	true	CLK	402	3870	4898	16	10	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_area_no1536	16	Area	false		false	CLK	413	3629	4791	16	3	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_spd_1536	16	Speed	false		true	CLK	402	3566	4944	16	4	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_spd_5g	16	Speed	false	true	true	CLK	402	3870	4898	16	10	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d16_spd_no1536	16	Speed	false		false	CLK	413	3629	4791	16	3	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d8_area_1536	8	Area	false		true	CLK	407	2905	3747	16	4	4	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d8_area_5g	8	Area	false	true	true	CLK	407	3223	3953	16	10	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	vu_1_d8_area_no1536	8	Area	false		false	CLK	407	2900	3618	16	3	4	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	1	vup_1_d16_area_1536	16	Area	false		true	CLK	560	3885	5009	16	4	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_area_5g	16	Area	false	true	true	CLK	560	4156	5101	16	10	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_area_no1536	16	Area	false		false	CLK	566	3897	4921	16	3	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_spd_1536	16	Speed	false		true	CLK	560	3885	5009	16	4	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_spd_5g	16	Speed	false	true	true	CLK	560	4156	5101	16	10	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d16_spd_no1536	16	Speed	false		false	CLK	566	3897	4921	16	3	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d8_area_1536	8	Area	false		true	CLK	566	3159	3957	16	4	4	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d8_area_5g	8	Area	false	true	true	CLK	555	3363	4067	16	10	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	vup_1_d8_area_no1536	8	Area	false		false	CLK	566	3165	3820	16	3	4	PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information			Configuration Parameters						Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	Data_Width	Speed_Optimization	Synchronous_Clear	Support_Size_5G	Support_Size_1536	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	1LV	zup_1_d16_area_1536	16	Area	false		true	CLK	456	3596	5028	16	4	4	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_d16_area_5g	16	Area	false	true	true	CLK	440	3809	5128	16	10	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_d16_area_no1536	16	Area	false		false	CLK	456	3612	4996	16	3	4	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_d16_spd_1536	16	Speed	false		true	CLK	456	3596	5028	16	4	4	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_d16_spd_5g	16	Speed	false	true	true	CLK	440	3809	5128	16	10	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_d16_spd_no1536	16	Speed	false		false	CLK	456	3612	4996	16	3	4	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_d8_area_1536	8	Area	false		true	CLK	456	2892	3906	16	4	4	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_d8_area_5g	8	Area	false	true	true	CLK	450	3217	4117	16	10	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	1LV	zup_1_d8_area_no1536	8	Area	false		false	CLK	440	2881	3854	16	3	4	PRODUCTION 1.30 05-15-2022

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