Performance and Resource Utilization for Binary Counter v12.0

Vivado Design Suite Release 2022.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 160 270 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 615 209 518 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 286 199 277 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_18_lut Fabric 18 false 1 UP false 2 CLK 752 22 29 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 675 22 30 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_47_lut Fabric 47 false 1 UP false 2 CLK 636 25 73 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 358 8 0 1 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_128_lut Fabric 128 false 1 UP false 8 CLK 658 175 270 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 642 209 500 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 352 199 305 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_18_lut Fabric 18 false 1 UP false 2 CLK 1008 20 29 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 730 22 30 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_47_lut Fabric 47 false 1 UP false 2 CLK 702 25 73 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 424 8 0 1 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 175 270 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 209 494 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 527 199 355 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1413 19 29 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1140 22 30 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1030 25 73 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 615 8 0 1 0 0 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_128_lut Fabric 128 false 1 UP false 8 CLK 680 220 270 0 0 0 PRODUCTION 2.10 2022-05-19
xcvc1902 vsva2197 1LP ver_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 675 263 496 0 0 0 PRODUCTION 2.10 2022-05-19
xcvc1902 vsva2197 1LP ver_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 336 269 386 0 0 0 PRODUCTION 2.10 2022-05-19
xcvc1902 vsva2197 1LP ver_1_18_lut Fabric 18 false 1 UP false 2 CLK 680 18 29 0 0 0 PRODUCTION 2.10 2022-05-19
xcvc1902 vsva2197 1LP ver_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 680 23 30 0 0 0 PRODUCTION 2.10 2022-05-19
xcvc1902 vsva2197 1LP ver_1_47_lut Fabric 47 false 1 UP false 2 CLK 680 50 73 0 0 0 PRODUCTION 2.10 2022-05-19
xcvc1902 vsva2197 1LP ver_1_48_dsp DSP48 48 false 1 UP false 2 CLK 680 0 0 1 0 0 PRODUCTION 2.10 2022-05-19
xcvc1902 vsva2197 1LP ver_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 680 0 0 1 0 0 PRODUCTION 2.10 2022-05-19
xcvc1902 vsva2197 1LP ver_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 391 16 0 1 0 0 PRODUCTION 2.10 2022-05-19

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 160 270 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 636 209 512 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 286 199 277 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_18_lut Fabric 18 false 1 UP false 2 CLK 785 23 29 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 730 22 30 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_47_lut Fabric 47 false 1 UP false 2 CLK 642 25 74 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 363 8 0 1 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_128_lut Fabric 128 false 1 UP false 8 CLK 713 175 271 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 647 209 494 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 352 199 305 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_18_lut Fabric 18 false 1 UP false 2 CLK 997 21 29 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 686 22 30 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_47_lut Fabric 47 false 1 UP false 2 CLK 680 25 73 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 429 8 0 1 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 176 270 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 209 494 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 511 199 349 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1419 20 29 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1156 22 30 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1047 25 73 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 599 8 0 1 0 0 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 176 270 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 636 209 494 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 402 199 345 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1041 21 29 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 844 22 30 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_47_lut Fabric 47 false 1 UP false 2 CLK 806 25 73 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 768 0 0 1 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 768 0 0 1 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 461 8 0 1 0 0 PRODUCTION 1.30 05-15-2022

COPYRIGHT

Copyright 2022 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed athttps://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed athttps://www.xilinx.com/legal.htm#tos.