Performance and Resource Utilization for AXI Protocol Converter v2.1

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix-7
Kintex-7
Kintex UltraScale
Kintex UltraScale+
Zynq UltraScale+

Artix-7

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a200t	fbg676	2	axi3_7a2	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	275	406	448	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	2	axi3_7a2_0	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	365	59	123	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	2	axi4lite_7a2	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	300	529	560	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	fbg676	2	axi4lite_7a2_0	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	594	36	10	0	0	0	PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k325t	ffg900	2	axi3_7k2	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	450	415	448	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	axi3_7k2_0	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	528	59	123	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	axi4lite_7k2	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	438	531	560	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	2	axi4lite_7k2_1	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	893	37	13	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	ffva1156	2	axi3_ku040	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	500	408	448	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	2	axi3_ku040_1	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	619	61	123	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	2	axi4lite_ku040	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	500	536	556	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	2	axi4lite_ku040_1	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	1055	35	9	0	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku5p	ffvb676	2	axi3_ku5p	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	707	423	448	0	0	0	PRODUCTION 1.29 05-01-2022
xcku5p	ffvb676	2	axi3_ku5p_0	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	934	62	123	0	0	0	PRODUCTION 1.29 05-01-2022
xcku5p	ffvb676	2	axi4lite_ku5p	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	744	580	556	0	0	0	PRODUCTION 1.29 05-01-2022
xcku5p	ffvb676	2	axi4lite_ku5p_0	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	1490	34	11	0	0	0	PRODUCTION 1.29 05-01-2022

Zynq UltraScale+

Part Information			Configuration Parameters							Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	SI_PROTOCOL	MI_PROTOCOL	READ_WRITE_MODE	TRANSLATION_MODE	DATA_WIDTH	ID_WIDTH	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	2	axi3_7z2_0	AXI4	AXI3	READ_WRITE	0	1024	4	aclk	924	62	123	0	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	2	axi3_7zu	AXI4	AXI3	READ_WRITE	2	1024	4	aclk	694	426	448	0	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	2	axi4lite_7z2_0	AXI4	AXI4LITE	READ_WRITE	0	64	4	aclk	1507	34	13	0	0	0	PRODUCTION 1.30 05-15-2022
xczu9eg	ffvb1156	2	axi4lite_7zu	AXI4	AXI4LITE	READ_WRITE	2	64	4	aclk	738	581	558	0	0	0	PRODUCTION 1.30 05-15-2022

COPYRIGHT

Copyright 2023 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.