Resource Utilization for AXI Chip2Chip Bridge v5.0

Vivado Design Suite Release 2022.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2022.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Kintex UltraScale

Part Information			Configuration Parameters				Resource Utilization
Device	Package	Speed Grade	Configuration Name	C_INTERFACE_TYPE	C_INSTANCE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku060	ffva1517	3	c2c_us_aurora	2	axi_c2c	aurora_init_clk=100 axi_c2c_phy_clk=100 s_aclk=250	970	1531	0	4	0	PRODUCTION 1.25 12-04-2018
xcku060	ffva1517	3	c2c_us_default		axi_c2c	axi_c2c_phy_clk=100 axi_c2c_selio_rx_clk_in=100 idelay_ref_clk=200 s_aclk=250	1007	1362	0	4	0	PRODUCTION 1.25 12-04-2018

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