Overview
Product Description
The Virtex™ 7 FPGA VC7215 Characterization Kit provides the hardware environment for characterizing and evaluating 80 GTH (13.1Gbps) transceivers of the on-board Virtex 7 V690T FPGA. The VC7215 allows evaluation of the Integrated Bit Error Ratio Test (IBERT) demonstration using the Vivado design suite. Each GTH Quad and its associated reference clock are routed from the FPGA to a connector pad which is designed to interface with a Samtec BullsEye connector. A cable enabled with a BullsEye connector and 10 standard SMAs allows users to connect to a broad range of evaluation platforms, from backplanes and optical evaluation boards to high speed test equipment. Each BullsEye connector handles a full GTH Quad, four transmit/receive pairs as well as the two independent reference clocks, enabling the highest level of flexibility in testing custom applications.
Key Features & Benefits
- Hardware environment for characterizing and evaluating 80 GTH (13.1Gbps) transceivers on the Virtex 7 V690T FPGAs
- Hardware, design tools, IP, and pre-verified reference designs
- Integrated Bit Error Ratio Test (IBERT) reference design
- System ACE™ SD controller
- Expand I/O with 3 FPGA Mezzanine Card (FMC) interface
- BullsEye connector supporting a full GTH Quad, with four transmit/receive pairs
- Twenty Samtec BullsEye connector pads for the GTH transceivers and reference clocks
- Two pairs of differential MRCC inputs with SMA connectors
Featured AMD Devices
Featuring the ROHS compliant kit including the Virtex 7 XC7VX690T-3FFG1927E FPGA
| Logic Cells | 693,120 |
|---|---|
| DSP Slices | 3,600 |
| Memory (Kb) | 52,920 |
| GTH 13.1 Gb/s Transceivers | 80 |
| I/0 Pins | 1,000 |
Product Information
Board Features
Featuring the VC7215 Characterization Board
Expansion Connectors
- Three VITA 57.1 FPGA mezzanine card (FMC) high pin count (HPC) connectors
Clocking
- Fixed, 200 MHz 2.5V LVDS oscillator wired to multi-region clock capable (MRCC) inputs
- SuperClock-2 module supporting multiple frequencies
Communication & Networking
- Twenty Samtec BullsEye connector pads for the GTH transceivers and reference clocks
- Two pairs of differential MRCC inputs with SMA connectors
- USB-to-UART bridge
Display
- Power status LEDs
- General purpose DIP switches, LEDs, push buttons, and test I/O
Configuration
- Digilent USB JTAG programming port
Memory
- System ACE™ SD controller
Control & I/O
- I2C Bus
Power
- PMBus connectivity to on-board digital power supplies
What's Inside
VC7215 Evaluation Board
Featuring the Virtex 7 XC7VX690T-3FFG1927E FPGA
Full seat Vivado™ Design Suite: Design Edition
Node locked & Device-locked to the Virtex 7 XC7VX690T FPGA, with 1 year of updates
Samtec Bullseye Cable with 10 standard SMAs
BullsEye Cable for AMD FPGA Characterization kits
Superclock-2 Module
Supporting Multiple Frequencies
Cables & Power Supply
Supply for all necessary voltages and power requirements
Resources
Design Tools
| Name | Description | License Type |
|---|---|---|
| Vivado Design Suite Design Edition | The AMD Vivado™ Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for FPGAs and SoCs. | Node locked & Device-locked to the Virtex 7 XC7VX690T FPGA, with 1 year of updates |