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(M3.9.24050.TableNoteNumberedCont.4.GTHE2.transceivers.only) 4011 0 R (M3.9.46217.TableNoteNumberedCont.3.For.the.supported.versions.of.the.tools.see.the.Xilinx.Design) 4012 0 R (M3.9.51550.TableNoteNumberedCont.3.2.2L.or.3) 4013 0 R (M3.9.55626.TableNoteNumbered.1.For.a.complete.list.of.supported.devices.see.Viva) 4014 0 R (M4.9.13380.XAnchorFigure.XRef.Target..Figure.1) 4015 0 R (M4.9.45251.XAnchorFigure.XRef.Target..Figure.12) 4016 0 R (M4.9.48951.Heading1.Unsupported.Features) 4017 0 R (M4.9.55839.XAnchorFigure.XRef.Target..Figure.11) 4018 0 R (M4.9.65101.Heading2.License.Checkers) 4019 0 R (M4.9.73301.XAnchorFigure.XRef.Target..Figure.14) 4020 0 R (M4.9.78952.XAnchorFigure.XRef.Target..Figure.16) 4021 0 R (M4.9.licencechk) 4022 0 R (M5.9.10264.Heading3.MDIO.Register.37.10G.PCS.Control.2) 4023 0 R (M5.9.10392.TableTitle.Table.112.Transceiver.Debug.Signals..UltraScale.Architectur) 4024 0 R (M5.9.11177.TableTitle.Table.650.AN.LP.Base.Page.Ability.Register.1.Bit.Definitions) 4025 0 R (M5.9.11761.TableTitle.Table.657.AN.LP.XNP.Ability.Register.2.Bit.Definitions) 4026 0 R (M5.9.11975.TableTitle.Table.622.10GBASER.FEC.Ability.Register.Bit.Definitions) 4027 0 R (M5.9.12303.Heading3.MDIO.Register.17.10G.PMAPMD.Control.2) 4028 0 R (M5.9.12771.TableTitle.Table.226.PCS.Status.1.Register.Bit.Definition) 4029 0 R (M5.9.13133.TableNoteNumbered.1.This.register.will.be.transferred.automatically.to) 4030 0 R (M5.9.14283.Heading3.MDIO.Register.748.Backplane.Ethernet.Status) 4031 0 R (M5.9.14407.Heading3.MDIO.Register.110.10G.PMD.Signal.Receive.OK) 4032 0 R (M5.9.15187.TableTitle.Table.229.10G.PCS.Control.2.Register.Bit.Definitions) 4033 0 R (M5.9.15889.TableTitle.Table.226.Version.Register) 4034 0 R (M5.9.16210.TableTitle.Table.213.10GBASEKR.LP.Coefficient.Update.Register.Bit.Defi) 4035 0 R (M5.9.16270.Heading1.Alignment.and.Synchronization.Status.Ports) 4036 0 R (M5.9.16314.TableTitle.Table.652.AN.XNP.Transmit.Register.0.Bit.Definitions) 4037 0 R (M5.9.16413.TableTitle.Table.627.10GBASER.FEC.Uncorrected.Blocks.Upper.Register.Bit.Definitions) 4038 0 R (M5.9.16902.TableTitle.Table.631.Configuration.Vector..BASER) 4039 0 R] >> endobj 3301 0 obj << /Limits [(M5.9.16996.TableNoteNumbered.1.This.input.is.4.bits.wide.for.the.GTHE3.transceive) (M5.9.43253.TableNoteNumberedCont.2.When.PFC.enabled.rxconfigurationvector.has.a.bus.width.367)] /Names [(M5.9.16996.TableNoteNumbered.1.This.input.is.4.bits.wide.for.the.GTHE3.transceive) 3912 0 R (M5.9.17042.TableTitle.Table.646.AN.Advertisement.Register.0.Bit.Definitions) 3913 0 R (M5.9.17351.XAnchorFigure.XRef.Target..Figure.23) 3914 0 R (M5.9.19975.TableTitle.Table.25.PMAPMD.Speed.Ability.Register.Bit.Definitions) 3915 0 R (M5.9.20147.Heading3.MDIO.Registers.35.and.36.PCS.Devices.in.Package) 3916 0 R (M5.9.20279.Heading1.Transceiver.Debug.Signals..Zynq7000.Virtex7.a) 3917 0 R (M5.9.21441.TableTitle.Table.632.Configuration.Vector..BASEKR.Specific) 3918 0 R (M5.9.21910.TableNoteNumbered.1.Only.valid.when.the.optional.FEC.block.is.included) 3919 0 R (M5.9.22126.XAnchorFigure.XRef.Target..Figure.21) 3920 0 R (M5.9.23626.TableNoteNumberedCont.2.Reset.controls.for.the.given.registers) 3921 0 R (M5.9.24290.TableNoteNumberedCont.3.Reset.controls.for.the.given.registers) 3922 0 R (M5.9.24617.TableNoteNumberedCont.2.Reset.controls.for.the.given.registers) 3923 0 R (M5.9.25062.TableNoteNumbered.1.saxistxtuser.is.00.when.not.using.1588.it.i) 3924 0 R (M5.9.25438.Heading1.Register.Space) 3925 0 R (M5.9.25457.TableTitle.Table.528.10GBASER.Test.Pattern.Error.Counter.Register.Bit.Definitions) 3926 0 R (M5.9.25726.TableTitle.Table.23.PMAPMD.Control.1.Register.Bit.Definitions) 3927 0 R (M5.9.25965.TableTitle.Table.37.Configuration.signals) 3928 0 R (M5.9.25980.TableNoteNumberedCont.5.If.FEC.Error.Passing.is.enabled.while.FEC.is.enabl) 3929 0 R (M5.9.27051.TableTitle.Table.243.PCS.Speed.Ability.Register.Bit.Definitions) 3930 0 R (M5.9.28338.TableNoteNumbered.1.When.PFC.enabled.txstatisticsvector.has.one.extr) 3931 0 R (M5.9.28434.TableTitle.Table.210.Statistic.Vector.Signals) 3932 0 R (M5.9.28733.XAnchorFigure.XRef.Target..Figure.26) 3933 0 R (M5.9.29365.TableTitle.Table.223.Transmitter.MTU.Configuration.Word) 3934 0 R (M5.9.30344.TableNoteNumbered.1.This.signal.has.no.meaning.or.effect.when.the.core) 3935 0 R (M5.9.30361.TableTitle.Table.230.10G.PCS.Status.2.Register.Bit.Definitions) 3936 0 R (M5.9.30472.Heading3.MDIO.Register.14.PMAPMD.Speed.Ability) 3937 0 R (M5.9.30746.TableTitle.Table.527.10GBASER.Test.Pattern.Control.Register.Bit.Definitions) 3938 0 R (M5.9.30842.TableTitle.Table.649.AN.LP.Base.Page.Ability.Register.0.Bit.Definitions) 3939 0 R (M5.9.31100.TableTitle.Table.616.10GBASEKR.PMD.Control.Register.Bit.Definitions) 3940 0 R (M5.9.31881.Heading3.MDIO.Register.30.PCS.Control.1) 3941 0 R (M5.9.32058.Heading3.Speeding.up.Simulation) 3942 0 R (M5.9.32092.TableTitle.Table.313.Transmit.Statistics.Vector.Bit.Description) 3943 0 R (M5.9.32309.TableNoteNumbered.1.These.reset.signals.should.be.asserted.for.a.single.clock.tick.only) 3944 0 R (M5.9.32886.TableNoteNumberedCont.2.These.registers.will.be.transferred.automatically) 3945 0 R (M5.9.32943.TableTitle.Table.222.Receiver.MTU.Configuration.Word) 3946 0 R (M5.9.33203.XAnchorFigure.XRef.Target..Figure.24) 3947 0 R (M5.9.33614.TableTitle.Table.715.MDIO.Configuration.Word.0) 3948 0 R (M5.9.33687.TableTitle.Table.31.Clientside.interface.ports..transmit) 3949 0 R (M5.9.35363.TableTitle.Table.658.Backplane.Ethernet.Status.Register.Bit.Definitions) 3950 0 R (M5.9.35491.TableNoteNumbered.1.If.FEC.Error.Passing.is.enabled.while.FEC.is.enabl) 3951 0 R (M5.9.35567.TableNoteNumberedCont.2.Only.valid.when.the.optional.AN.block.is.included) 3952 0 R (M5.9.36075.TableNoteNumbered.1.Txxxhis.reset.will.also.reset.all.management.regis) 3953 0 R (M5.9.36089.TableTitle.Table.27.Optical.Module.Interface.Ports) 3954 0 R (M5.9.36260.TableTitle.Table.210.10G.PMD.Signal.Receive.OK.Register.Bit.Definitions) 3955 0 R (M5.9.36333.TableTitle.Table.27.10G.PMAPMD.Control.2.Register.Bit.Definitions) 3956 0 R (M5.9.36434.Heading3.MDIO.Register.725.26.27.AN.LP.XNP.Ability) 3957 0 R (M5.9.37457.TableTitle.Table.645.AN.Status.Register.Bit.Definitions) 3958 0 R (M5.9.37490.XAnchorFigure.XRef.Target..Figure.558) 3959 0 R (M5.9.38087.TableNoteNumbered.1.For.UltraScale.devices.the.DCLK.must.be.freerunni) 3960 0 R (M5.9.38184.TableTitle.Table.619.10GBASEKR.LP.Status.Register.Bit.Definitions) 3961 0 R (M5.9.39094.TableTitle.Table.38.Clock.and.Reset.Ports.Virtex6) 3962 0 R (M5.9.39326.TableTitle.Table.526.10GBASER.Test.Pattern.Seed.B03.Register.Bit.Definitions) 3963 0 R (M5.9.39519.TableNoteNumbered.1.BaseR.Set.from.pmapmdtype.port.BASEKR.retur) 3964 0 R (M5.9.39578.TableNoteNumberedCont.2.Tie.reserved.signals.to.0) 3965 0 R (M5.9.40010.TableTitle.Table.644.AN.Control.Register.Bit.Definitions) 3966 0 R (M5.9.40443.TableTitle.Table.524.10GBASER.Status.Register.2.Bit.Definitions) 3967 0 R (M5.9.40486.TableNoteNumbered.1.Cleared.when.read) 3968 0 R (M5.9.40576.TableTitle.Table.89.DRP.Interface.Signals) 3969 0 R (M5.9.41471.TableTitle.Table.212.10GBASEKR.PMD.Status.Register.Bit.Definitions) 3970 0 R (M5.9.41540.TableNoteNumbered.1.This.signal.should.be.asserted.for.at.most.3.cycle) 3971 0 R (M5.9.41840.XAnchorFigure.XRef.Target..Figure.610) 3972 0 R (M5.9.42359.TableTitle.Table.29.Clock.and.Reset.Ports..Zynq7000.Virtex7.and.Kintex7De) 3973 0 R (M5.9.43027.TableNoteNumbered.1.These.reset.signals.should.be.asserted.for.a.single.clock.tick.only) 3974 0 R (M5.9.43253.TableNoteNumberedCont.2.When.PFC.enabled.rxconfigurationvector.has.a.bus.width.367) 3975 0 R] >> endobj 3302 0 obj << /Limits [(M5.9.43264.TableTitle.Table.224.Per.Priority.QuantaRefresh.Register.0x4800x49C) (M5.9.71707.TableTitle.Table.629.Vendorspecific.LD.Training.Register.Bit.Definitions)] /Names [(M5.9.43264.TableTitle.Table.224.Per.Priority.QuantaRefresh.Register.0x4800x49C) 3848 0 R (M5.9.43738.TableNoteNumbered.1.For.UltraScale.devices.the.DCLK.must.be.freerunni) 3849 0 R (M5.9.44673.Heading1.Register.Space) 3850 0 R (M5.9.44834.Heading3.MDIO.Register.365522.RX.Fixed.Latency.Fractiona) 3851 0 R (M5.9.46183.TableNoteNumbered.1.Latched.when.1174.is.read.Cleared.when.read) 3852 0 R (M5.9.46499.TableNoteNumberedCont.2.Depends.on.core.generation.parameters) 3853 0 R (M5.9.46602.TableTitle.Table.16.Tx.Buffer.BypassManual.Phase.Alignment.Ports) 3854 0 R (M5.9.48327.TableTitle.Table.27.IEEE1588.System.Timer.Ports) 3855 0 R (M5.9.48385.TableTitle.Table.231.10GBASER.Status.Register.1.Bit.Definitions) 3856 0 R (M5.9.48615.TableNoteNumberedCont.2.If.FEC.is.enabled.during.autonegotiation.then.thi) 3857 0 R (M5.9.48888.TableNoteNumberedCont.2.Only.bits.90.are.writable) 3858 0 R (M5.9.49257.TableNoteNumberedCont.2.For.cores.with.optional.AN.block) 3859 0 R (M5.9.49496.TableNoteNumbered.1.All.signals.are.synchronous.to.txclk0) 3860 0 R (M5.9.49926.TableNoteNumberedCont.2.If.FEC.is.enabled.during.autonegotiation.then.thi) 3861 0 R (M5.9.50203.TableTitle.Table.88.DRP.Interface.Ports) 3862 0 R (M5.9.50993.XAnchorFigure.XRef.Target..Figure.557) 3863 0 R (M5.9.51429.TableTitle.Table.311.Training.Interface.Ports..V7K7.FPGAs.BASEKR.only) 3864 0 R (M5.9.51557.TableNoteNumbered.1.This.bit.is.a.constant.and.clock.domain.is.not.app) 3865 0 R (M5.9.51752.TableNoteNumberedCont.2.Tie.reserved.signals.to.0) 3866 0 R (M5.9.51790.TableNoteNumberedCont.4.Toggle.to.load.the.AN.Page.data.from.the.associate) 3867 0 R (M5.9.52018.TableNoteNumberedCont.4.This.bit.is.a.logical.OR.of.two.latching.bits.and) 3868 0 R (M5.9.52191.TableTitle.Table.244.AN.Advertisement.Register.1.Bit.Definitions) 3869 0 R (M5.9.52322.Heading3.MDIO.Register.10.PMAPMD.Control.1) 3870 0 R (M5.9.52629.TableNoteNumbered.1.When.an.optical.module.is.present.the.logical.NOR) 3871 0 R (M5.9.52826.Heading3.MDIO.Register.365520.IEEE1588.Control) 3872 0 R (M5.9.53222.TableTitle.Table.651.AN.LP.Base.Page.Ability.Register.2.Bit.Definitions) 3873 0 R (M5.9.53228.TableNoteNumberedCont.3.The.latter.two.signals.are.required.in.the.core.to) 3874 0 R (M5.9.53388.Heading3.MDIO.Register.71.AN.Status) 3875 0 R (M5.9.53621.TableTitle.Table.714.MDIO.Configuration.Registers) 3876 0 R (M5.9.53627.TableTitle.Table.39.Interrupt.Registers) 3877 0 R (M5.9.54767.TableTitle.Table.3.Configuration.and.Status.Vectors) 3878 0 R (M5.9.54945.TableNoteNumberedCont.2.When.PFC.enabled.rxstatisticsvector.has.one.extr) 3879 0 R (M5.9.55267.TableTitle.Table.634.Status.Vector..BASEKR.Specific) 3880 0 R (M5.9.58115.TableNoteNumbered.1.These.registers.are.programmed.by.writing.to.regis) 3881 0 R (M5.9.59273.TableTitle.Table.26.PMAPMD.Devices.in.Package.Registers.Bit.Definitio) 3882 0 R (M5.9.59629.Heading3.MDIO.Register.31.PCS.Status.1) 3883 0 R (M5.9.59782.TableNoteNumbered.1.This.value.is.different.for.each.1588.permutation) 3884 0 R (M5.9.60708.Heading3.MDIO.Register.332768.VendorSpecific.PCS.Loopbac) 3885 0 R (M5.9.60953.TableTitle.Table.233.10GBASER.Test.Pattern.Seed.A02.Register.Bit.Defi) 3886 0 R (M5.9.61216.TableNoteNumbered.1.All.signals.are.synchronous.to.rxclk0) 3887 0 R (M5.9.62527.TableTitle.Table.26.Signal.Definition) 3888 0 R (M5.9.63112.TableTitle.Table.21.10GBASER.PCSPMA.MDIO.Registers) 3889 0 R (M5.9.63223.TableTitle.Table.633.Status.Vector..BASER) 3890 0 R (M5.9.63895.Heading3.MDIO.Register.1154.10GBASEKR.LD.Coefficient.Upd) 3891 0 R (M5.9.64275.TableTitle.Table.210.Miscellaneous.Signals) 3892 0 R (M5.9.65139.TableTitle.Table.718.MDIO.RX.Data) 3893 0 R (M5.9.65188.TableNoteNumbered.1.Only.bits.30.are.writable) 3894 0 R (M5.9.65613.TableTitle.Table.28.10G.PMAPMD.Status.2.Register.Bit.Definitions) 3895 0 R (M5.9.66065.TableNoteNumbered.1.Writable.only.when.register.11501..0) 3896 0 R (M5.9.66157.TableTitle.Table.216.Receiver.Configuration.Word.0) 3897 0 R (M5.9.67533.TableTitle.Table.624.10GBASER.FEC.Corrected.Blocks.lower.Register.Bit.Definitions) 3898 0 R (M5.9.67673.TableTitle.Table.225.PCS.Control.1.Register.Bit.Definitions) 3899 0 R (M5.9.68421.TableTitle.Table.225.Legacy.Pause.Refresh.Register.0x4A0) 3900 0 R (M5.9.68436.TableTitle.Table.219.Transmitter.Configuration.Word) 3901 0 R (M5.9.68865.ChapterTitle.Product.Specification) 3902 0 R (M5.9.69387.TableTitle.Table.227.Capability.Register) 3903 0 R (M5.9.69925.TableNoteNumberedCont.2.Only.valid.when.the.optional.AN.block.is.included) 3904 0 R (M5.9.70016.Heading3.MDIO.Register.1150.10GBASEKR.PMD.Control) 3905 0 R (M5.9.71155.TableNoteNumbered.1.x41.for.version.41.of.core) 3906 0 R (M5.9.71204.Heading3.MDIO.Register.38.10G.PCS.Status.2) 3907 0 R (M5.9.71227.TableTitle.Table.314.Receive.Statistics.Vector.Description) 3908 0 R (M5.9.71407.Heading3.MDIO.Register.365535.125.ms.Timer.Control..Virtex7Kinte) 3909 0 R (M5.9.71683.TableNoteNumbered.1.When.PFC.enabled.txconfigurationvector.has.a.bus.width.367) 3910 0 R (M5.9.71707.TableTitle.Table.629.Vendorspecific.LD.Training.Register.Bit.Definitions) 3911 0 R] >> endobj 3303 0 obj << /Limits [(M5.9.71713.TableTitle.Table.32.Clientside.interface.ports..receive) (M5.9.RegisterSpace)] /Names [(M5.9.71713.TableTitle.Table.32.Clientside.interface.ports..receive) 3784 0 R (M5.9.72371.TableTitle.Table.33.Flow.control.interface.ports) 3785 0 R (M5.9.72856.TableNoteNumberedCont.2.This.bit.is.a.constant.and.clock.domain.is.not.app) 3786 0 R (M5.9.73050.Heading3.MDIO.Register.1171.10GBASER.FEC.Control) 3787 0 R (M5.9.73158.XAnchorFigure.XRef.Target..Figure.611) 3788 0 R (M5.9.73262.TableTitle.Table.24.PMAPMD.Status.1.Register.Bit.Definitions) 3789 0 R (M5.9.73671.Heading1.Resource.Utilization) 3790 0 R (M5.9.73830.Heading3.MDIO.Register.11.PMAPMD.Status.1) 3791 0 R (M5.9.74048.TableTitle.Table.653.AN.XNP.Transmit.Register.1.Bit.Definitions) 3792 0 R (M5.9.74064.TableNoteNumbered.1.Latched.when.1172.is.read.Cleared.when.read) 3793 0 R (M5.9.75197.TableNoteNumberedCont.2.In.fact.this.is.equivalent.to.Training.Done.AND.signal) 3794 0 R (M5.9.75211.TableNoteNumbered.1.This.output.is.8bits.wide.for.the.GTXE2.transceiv) 3795 0 R (M5.9.75423.TableNoteNumbered.1.Cleared.when.read) 3796 0 R (M5.9.75563.TableNoteNumbered.1.Only.valid.when.the.optional.FEC.block.is.included) 3797 0 R (M5.9.76643.TableTitle.Table.213.Transceiver.Debug.Signals) 3798 0 R (M5.9.76820.TableTitle.Table.722.configurationvectorrx.Bit.Definitions) 3799 0 R (M5.9.77225.TableNoteNumbered.1.This.bit.is.equivalent.to.the.FEC.block.lock.if.FE) 3800 0 R (M5.9.77316.Heading3.MDIO.Register.19.10G.PMD.Transmit.Disable) 3801 0 R (M5.9.78071.TableNoteNumbered.1.This.is.tied.to.0.for.Virtex6.FPGA.BASER.core) 3802 0 R (M5.9.78075.TableTitle.Table.228.PCS.Devices.in.Package.Registers.Bit.Definitions) 3803 0 R (M5.9.78166.Heading1.Port.Descriptions) 3804 0 R (M5.9.80411.TableTitle.Table.218.Receiver.Configuration.Word.1) 3805 0 R (M5.9.80559.TableTitle.Table.28.Correction.Field.System.Timer.Ports) 3806 0 R (M5.9.80609.Heading3.MDIO.Register.18.10G.PMAPMD.Status.2) 3807 0 R (M5.9.81045.TableNoteNumberedCont.2.This.signal.is.not.connected.inside.this.version.o) 3808 0 R (M5.9.81752.TableNoteNumbered.1.0x0080.when.the.core.is.generated.with.1Step.supp) 3809 0 R (M5.9.82329.TableTitle.Table.245.AN.Advertisement.Register.2.Bit.Definitions) 3810 0 R (M5.9.82507.TableTitle.Table.72.Statistics.Counters) 3811 0 R (M5.9.82784.TableTitle.Table.211.Interrupt.Output.Port.Description) 3812 0 R (M5.9.82794.Heading3.MDIO.Register.332.10GBASER.Status.1) 3813 0 R (M5.9.84525.Heading3.MDIO.Register.34.PCS.Speed.Ability) 3814 0 R (M5.9.85448.TableTitle.Table.656.AN.LP.XNP.Ability.Register.1.Bit.Definitions) 3815 0 R (M5.9.85674.TableNoteNumbered.1.For.simulation.purposes.only.to.disable.AN.at.sta) 3816 0 R (M5.9.85753.TableTitle.Table.73.Configuration.Registers) 3817 0 R (M5.9.85830.TableNoteNumbered.1.For.cores.with.optional.FEC.block) 3818 0 R (M5.9.86336.TableTitle.Table.210.Transmitted.Timestamp.Adjustment.Control.Register) 3819 0 R (M5.9.86646.Heading3.MDIO.Register.1170.10GBASER.FEC.Ability) 3820 0 R (M5.9.86846.Heading3.MDIO.Register.342.10GBASER.Test.Pattern.Control) 3821 0 R (M5.9.87110.Heading3.MDIO.Register.70.AN.Control) 3822 0 R (M5.9.87394.TableTitle.Table.221.10GBASER.FEC.Uncorrected.Blocks.Lower.Register) 3823 0 R (M5.9.87666.TableTitle.Table.26.Management.Interface.Port.Descriptions.Contd) 3824 0 R (M5.9.88342.Heading3.MDIO.Registers.15.and.16.PMAPMD.Devices.in.Pac) 3825 0 R (M5.9.89037.TableTitle.Table.220.Flow.Control.Configuration.Register.0x40C.Contd) 3826 0 R (M5.9.90013.TableTitle.Table.224.Core.Version.Information) 3827 0 R (M5.9.90101.TableTitle.Table.25) 3828 0 R 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/Length 2793 /Subtype /XML /Type /Metadata >> stream application/pdf This subsystem provides a 10-Gigabit Ethernet MAC and a 10-Gigabit Ethernet PCS/PMA in 10GBASE-R and 10GBASE-KR modes to provide an IEEE1588-compatible 10-Gigabit Ethernet port. 10 Gigabit Ethernet Subsystem v3.1 Product Guide Xilinx, Inc. Acrobat Distiller 15.0 (Windows) UltraScale, sub-system, GigE, 10-GB, 10-GigE, 10-Gigabit, Ethernet, Vivado, IP Integrator, IPI, PCS/PMA, XGMAC, IEEE1588, Zynq, Zynq-7000, Virtex, Virtex-7, Kintex, Kintex-7, AXI4-Lite, AXI4-Stream, 10GBASE-R,10BASE-KR FrameMaker 2019.0.5 2021-02-03T11:46:37Z uuid:d7c9cf4f-2707-453f-8aab-004a69982b1e uuid:7df72b51-b1bd-4338-b9a6-2698c74da920 2021-02-03T11:56:47+05:30 endstream endobj 11494 0 obj << /Author (Xilinx, Inc.) /CreationDate (D:20210203114637Z) /Creator (FrameMaker 2019.0.5) /Keywords (UltraScale, sub-system, GigE, 10-GB, 10-GigE, 10-Gigabit, Ethernet, Vivado, IP Integrator, IPI, PCS/P\ MA, XGMAC, IEEE1588, Zynq, Zynq-7000, Virtex, Virtex-7, Kintex, Kintex-7, AXI4-Lite, AXI4-Stream, 10G\ BASE-R,10BASE-KR ) /ModDate (D:20210203115647+05'30') /PostProcess (v2020.2.0.1) /Producer (Xilinx, Inc. via ABCpdf) /Subject (This subsystem provides a 10-Gigabit Ethernet MAC and a 10-Gigabit Ethernet PCS/PMA in 10GBASE-R and \ 10GBASE-KR modes to provide an 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